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authorCliff Click <cliffc@acm.org>2026-09-29 12:34:58 -0700
committerCliff Click <cliffc@acm.org>2026-09-29 12:34:58 -0700
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commit 3ba6686fc991998a0a420709dfb0012bbddf77ab Author: Cliff Click <cliffc@acm.org> Date: Tue Sep 29 12:21:46 2026 -0700 Backport lazy memory splits to ch10, split into ch10a and b commit fa7d56f72455828826d0ab7e1c142ca814e6e2aa Author: Cliff Click <cliffc@acm.org> Date: Tue Sep 29 10:10:53 2026 -0700 Reverse edges commit e1bba17ff54400a34ede0eaacad863420d021119 Author: Cliff Click <cliffc@acm.org> Date: Tue Sep 29 09:44:41 2026 -0700 Split ch10 Basic memory introduction in 10a, then precise aliases in 10b.
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+digraph Memory {
+ rankdir=RL;
+ node [shape=box];
+ P [label="Phi(memory)"];
+ S [label="Loop-body Store"];
+ P -> Entry [color=blue];
+ P -> S [color=blue,constraint=false]; // Backedge must not place Store before Phi.
+ S -> P [color=blue];
+ P -> Loop [style=dashed]; Return -> P [color=blue];
+ Return -> S [style=invis]; // Layout only: Phi, Store, Return from left to right.
+}