Ch19 (#155)

* Initial push

Major CodeGen cleanup; most static globals move into the CodeGen object.

* Minor progress bug with mutual recursion

* Add test from pr#148

* First cut x86 "port"

Only "return 0;", no registers, no encoding, but yah gotta start somewhere

* Update README.md

* Update README.md

* Update ListScheduler.java

* command line launcher for simple

Parser bug fref in args
Some new test cases.

* Add basic RegMask for more than 64 bits of register mask.

Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension

* ASM Printer

InstSel handles folding 2+ ideal ops into 1 machine op

* handle instSel for some control flow

Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.

* Basic if-block inst selects and asm prints

* Add mul-by-coinstant to shift

* left shift codegen basic

* exclude RSP from *write* mask

* 2-arg add (not immediate)

mul-by-small constant opt.  Some utilities.

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* inst select for new struct allocation

* Float, bitwise and arithmetic operands codegen x86-64 (#150)

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* float ops without imm values

* merge

* merge

* inst select for new struct allocation

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* float ops without imm values

* merge

* merge

* Rebased on ch 19

* Update tests

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* cleanup after merge

alpha-sort helper fcns
implicit test vs zero/null

* Add LEA op

asm print works on ideal nodes for all tests

* Minor cleanup lea

* x86 addressing modes during inst select

Drop New taking inits; just follow with initializing stores.  Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate

* extended ch13, 14,15,16 (#153)

* merge2

* merge3

* Fix a few minor fuzzer bugs

* Force array layout

ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.

* Fix a bunch of float issues

was deleting required inputs

* simpler invariant

defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).

* Call & CallR X86 instructions

* Add-from-memory op

Remove FP immediate forms.

* Remove name from TFP

Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.

* New (#154)

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* call setup

* merge2

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Add CmpMem form

Common addressing mode print
LEA can skip a base

* Add a AddFMemX86

A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.

* Docs

* XMM reg mask fix

Minor README updates

* Allow inverted cmp/mem

narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info

* Support "*ptr op= val"

at least for MemAdd

* missed golden rule update

* Array len is u32

load-after-store zero/sign-extends if the store is truncating

* One more missed case

---------

Co-authored-by: hadha <helsgithub15@gmail.com>
Co-authored-by: Tamás Hadházy <85063808+Hels15@users.noreply.github.com>

1 files changed, 85 insertions, 0 deletions

diff --git a/chapter19/docs/lattice2.gv b/chapter19/docs/lattice2.gv
new file mode 100644
index 00000000..6aa37fa0
--- /dev/null
+++ b/chapter19/docs/lattice2.gv
@@ -0,0 +1,85 @@
+digraph Lattice {
+    compound = true;
+    // Define nodes
+    splines=false;
+    node [shape=oval, style=filled];
+    nodesep=0.2;
+    ranksep=0.4;
+
+    TOP [label="~scalar\n+int+tmp+0", fillcolor=black, fontcolor=white, group=center];
+
+    // ------------------------
+    PTRHQ [label="~tmp\n+tmp+0", fillcolor=green, fontcolor=white, group=left];
+    TOP -> PTRHQ
+
+    VALH_ [label="~nscalar\n+int+tmp", fillcolor=white, group=center];
+    TOP -> VALH_
+
+    INTHQ [label="~int\n+int+0", fillcolor=lightblue, group=right];
+    TOP -> INTHQ
+
+    LEFTHI [label="junk", style=invis, group=junkleft]
+  
+
+    PTRHQ -> LEFTHI-> VALH_ -> INTHQ [style=invis];
+    { rank=same; PTRHQ; LEFTHI; VALH_; INTHQ }
+
+    // ------------------------
+    PTRH_ [label="~ntmp\n+tmp", fillcolor=green, fontcolor=white, group=left];
+    VALH_ -> PTRH_
+    PTRHQ -> PTRH_
+
+    INTH_ [label="~nint\n+int", fillcolor=lightblue, group=right];
+    VALH_ -> INTH_
+    INTHQ -> INTH_
+    { rank=same; PTRH_; INTH_ }
+
+    // ------------------------
+    NILX_ [label="~nil\n[int,tmp]+0", fillcolor=aqua, group=junkleft];
+    INTHQ -> NILX_
+    PTRHQ -> NILX_
+    
+    NIL__ [label="nil\n[+int+tmp],0", fillcolor=pink];
+    VALH_ -> NIL__;
+    
+    NILX_ -> NIL__  [style=invis];
+    { rank=same; NIL__; NILX_ }
+
+    // ------------------------
+    PTRL_ [label="ntmp\ntmp", fillcolor=green, fontcolor=white, group=left];
+    PTRH_ -> PTRL_
+
+    INTL_ [label="nint\nint", fillcolor=lightblue, group=right];
+    INTH_ -> INTL_
+    { rank=same; PTRL_; INTL_ }
+    
+    // ------------------------
+    PTRL0 [label="tmp\ntmp,0", fillcolor=green, fontcolor=white, group=left];
+    PTRL_ -> PTRL0
+    NIL__ -> PTRL0
+
+    VALL_ [label="nscalar\nint,tmp", fillcolor=white, group=center];
+    PTRL_ -> VALL_
+    INTL_ -> VALL_
+    NILX_ -> VALL_
+
+    INTL0 [label="int\nint,0", fillcolor=lightblue, group=right];
+    INTL_ -> INTL0
+    NIL__ -> INTL0
+
+    PTRL0 -> VALL_ -> INTL0 [style=invis];
+    { rank=same; PTRL0; VALL_; INTL0 }
+
+    // ------------------------
+    BOT [label="scalar\nint,tmp,0", fillcolor=black, fontcolor=white, group=center];
+    PTRL0 -> BOT
+    INTL0 -> BOT
+    VALL_ -> BOT
+
+    // ------------------------
+    // Verticle alignment
+    TOP -> VALH_ -> VALL_ -> BOT [style=invis];
+    PTRHQ -> PTRH_ -> PTRL_ -> PTRL0 [style=invis];
+    INTHQ -> INTH_ -> INTL_ -> INTL0 [style=invis];
+    LEFTHI -> NILX_ [style=invis]
+}