Push a driver for ARM logical 12-bit immediates

3 files changed, 16 insertions, 4 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java
index 68550926..3f72f026 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java
@@ -14,7 +14,7 @@ public class OrIARM extends MachConcreteNode implements MachNode {
     @Override public String op() { return "ori"; }
     @Override public RegMask regmap(int i) { return arm.RMASK; }
     @Override public RegMask outregmap() { return arm.RMASK; }
-    @Override public void encoding( Encoding enc ) { arm.imm_inst(enc,this,170,_imm); }
+    @Override public void encoding( Encoding enc ) { arm.imm_inst(enc,this,0xC8,_imm); }
     // General form: "ori  rd = rs1 | imm"
     @Override public void asm(CodeGen code, SB sb) {
         sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" | #").p(_imm);
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
index 6fc0afec..add609fc 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
@@ -164,8 +164,19 @@ public class arm extends Machine {
         return ti.isConstant() && ((ti.value()<<52)>>52) == ti.value();
     }
 
+
+    // Can we encode this in ARM's 12-bit LOGICAL immediate form?
+    // Some combination of shifted bit-masks.
+    private static int imm12Logical(TypeInteger ti) {
+        if( !ti.isConstant() ) return -1;
+        // TODO: THE REAL THING
+        // INVARIANT: always a positive thing
+        return -1;
+    }
+
     // sh is encoded in opcdoe
     public static int imm_inst(int opcode, int imm12, int rn, int rd) {
+        assert opcode >=0 && imm12 >= 0 && rn >=0 && rd>=0; // Caller zeros high order bits
         return (opcode << 22) | (imm12 << 10) | (rn << 5) | rd;
     }
     public static void imm_inst(Encoding enc, Node n, int opcode, int imm12) {
@@ -477,8 +488,9 @@ public class arm extends Machine {
     }
 
     private Node or(OrNode or) {
-        return or.in(2) instanceof ConstantNode off && off._con instanceof TypeInteger ti && imm12(ti)
-            ? new OrIARM(or, (int)ti.value())
+        int imm12;
+        return or.in(2) instanceof ConstantNode off && off._con instanceof TypeInteger ti && (imm12 = imm12Logical(ti)) != -1
+            ? new OrIARM(or, imm12)
             : new OrARM(or);
     }
 
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
index 42f34d85..9f89f983 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
@@ -20,7 +20,7 @@ public class RetRISC extends ReturnNode implements MachNode{
     @Override public RegMask regmap(int i) { return riscv.retMask(_fun.sig(),i); }
     @Override public RegMask outregmap() { return null; }
     @Override public void encoding( Encoding enc ) {
-        short rpc = enc.reg(this);
+        short rpc = enc.reg(rpc());
         int body = riscv.i_type(0x67, riscv.ZERO, 0, rpc, 0);
         enc.add4(body);
     }