Make more public

Allows custom risc5 to override

4 files changed, 6 insertions, 5 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/MachNode.java b/chapter21/src/main/java/com/seaofnodes/simple/node/MachNode.java
index 5486b1c1..f63b3651 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/MachNode.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/MachNode.java
@@ -44,7 +44,7 @@ public interface MachNode {
     // Make a clone of a cheap instruction
     default Node copy() { return null; }
 
-    // Encoding is appended into the byte array; size is returned
+    // Encoding is appended, relocations gathered.
     void encoding( Encoding enc );
 
     // Human-readable form appended to the SB.  Things like the encoding,
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/BranchRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/BranchRISC.java
index a4c15c0c..6325c90d 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/BranchRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/BranchRISC.java
@@ -9,7 +9,7 @@ import java.util.BitSet;
 public class BranchRISC extends IfNode implements MachNode, RIPRelSize {
     String _bop;
     // label is obtained implicitly
-    BranchRISC( IfNode iff, String bop, Node n1, Node n2 ) {
+    public BranchRISC( IfNode iff, String bop, Node n1, Node n2 ) {
         super(iff);
         _bop = bop;
         _inputs.setX(1,n1);
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java
index 9d21ae13..1378d0f9 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java
@@ -10,6 +10,7 @@ import com.seaofnodes.simple.type.TypeInteger;
 // selection by adding with a LUI.
 public class IntRISC extends ConstantNode implements MachNode {
     IntRISC(ConstantNode con) { super(con); }
+    public IntRISC(TypeInteger con) { super(con); }
     @Override public String op() { return "ldi"; }
     @Override public RegMask regmap(int i) { return null; }
     @Override public RegMask outregmap() { return riscv.WMASK; }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index 9bf560cf..9d878b43 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -69,7 +69,7 @@ public class riscv extends Machine {
     public static RegMask A6_MASK = new RegMask(A6);
     public static RegMask A7_MASK = new RegMask(A7);
 
-    static final RegMask RPC_MASK = new RegMask(RPC);
+    public static final RegMask RPC_MASK = new RegMask(RPC);
 
     // Float arguments masks
     public static RegMask FA0_MASK = new RegMask(FA0);
@@ -328,12 +328,12 @@ public class riscv extends Machine {
     }
 
     // True if signed 12-bit immediate
-    private static boolean imm12(TypeInteger ti) {
+    public static boolean imm12(TypeInteger ti) {
         // 52 = 64-12
         return ti.isConstant() && ((ti.value()<<52)>>52) == ti.value();
     }
     // True if HIGH 20-bit signed immediate, with all zeros low.
-    static boolean imm20Exact(TypeInteger ti) {
+    public static boolean imm20Exact(TypeInteger ti) {
         // shift left 32 to clear out the upper 32 bits.
         // shift right SIGNED to sign-extend upper 32 bits; then shift 12 more to clear out lower 12 bits.
         // shift left 12 to re-center the bits.