Minor cleanups

Custom op for risc5, a few more things public for external port

5 files changed, 17 insertions, 12 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegMask.java b/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegMask.java
index f28805b5..2dbb23a9 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegMask.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegMask.java
@@ -84,7 +84,7 @@ public class RegMask {
 
     boolean isEmpty() { return _bits0==0 && _bits1==0; }
 
-    boolean test( int reg ) {
+    public boolean test( int reg ) {
         return ((reg<64 ? (_bits0 >> reg) : (_bits1 >> (reg-64))) & 1)  != 0;
     }
 
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/MemOpNode.java b/chapter21/src/main/java/com/seaofnodes/simple/node/MemOpNode.java
index de27bc75..0a1065f1 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/MemOpNode.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/MemOpNode.java
@@ -9,6 +9,12 @@ import java.util.BitSet;
 
 /**
  * Convenience common base for Load and Store.
+ *
+ * 0 - Control
+ * 1 - Memory
+ * 2 - Base of object, OOP
+ * 3 - Offset, integer types
+ * 4 - Value, for Stores only
  */
 public abstract class MemOpNode extends Node {
 
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java
index ffa173ef..1a179556 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java
@@ -22,7 +22,7 @@ public abstract class MemOpRISC extends MemOpNode implements MachNode {
     @Override public String label() { return op(); }
     Node val() { return in(4); } // Only for stores
 
-    @Override public  StringBuilder _printMach(StringBuilder sb, BitSet visited) { return sb.append(".").append(_name); }
+    @Override public StringBuilder _printMach(StringBuilder sb, BitSet visited) { return sb.append(".").append(_name); }
 
     @Override public Type compute() { throw Utils.TODO(); }
     @Override public Node idealize() { throw Utils.TODO(); }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
index 1e501411..41503da9 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
@@ -8,10 +8,13 @@ import com.seaofnodes.simple.node.FunNode;
 import com.seaofnodes.simple.node.ReturnNode;
 import com.seaofnodes.simple.node.MachNode;
 
-public class RetRISC extends ReturnNode implements MachNode{
-    RetRISC(ReturnNode ret, FunNode fun) { super(ret, fun); fun.setRet(this); }
+public class RetRISC extends ReturnNode implements MachNode {
+    public RetRISC(ReturnNode ret, FunNode fun) {
+        super(ret, fun);
+        if( fun != null ) fun.setRet(this);
+    }
     @Override public String op() {
-        return ((FunRISC)fun())._frameAdjust > 0 ? "addi" : "ret";
+        return fun()._frameAdjust > 0 ? "addi" : "ret";
     }
     // Correct Nodes outside the normal edges
     @Override public void postSelect(CodeGen code) {
@@ -22,7 +25,7 @@ public class RetRISC extends ReturnNode implements MachNode{
     @Override public RegMask regmap(int i) { return riscv.retMask(_fun.sig(),i); }
     @Override public RegMask outregmap() { return null; }
     @Override public void encoding( Encoding enc ) {
-        int frameAdjust = ((FunRISC)fun())._frameAdjust;
+        int frameAdjust = fun()._frameAdjust;
         if( frameAdjust > 0 )
             enc.add4(riscv.i_type(riscv.I_TYPE, riscv.SP, 0, riscv.SP, (frameAdjust*-8) & 0xFFF));
         short rpc = enc.reg(rpc());
@@ -30,7 +33,7 @@ public class RetRISC extends ReturnNode implements MachNode{
     }
 
     @Override public void asm(CodeGen code, SB sb) {
-        int frameAdjust = ((FunRISC)fun())._frameAdjust;
+        int frameAdjust = fun()._frameAdjust;
         if( frameAdjust>0 )
             sb.p("rsp += #").p(frameAdjust*-8).p("\nret");
         // Post code-gen, just print the "ret"
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index 9d878b43..2aa39210 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -5,8 +5,6 @@ import com.seaofnodes.simple.codegen.*;
 import com.seaofnodes.simple.node.*;
 import com.seaofnodes.simple.type.*;
 
-import java.io.ByteArrayOutputStream;
-
 public class riscv extends Machine {
 
     public riscv(CodeGen code) {
@@ -107,6 +105,7 @@ public class riscv extends Machine {
     // major opcode: OP
     public static int OP    = 0b01_100_11;
     public static int OP_FP = 0b10_100_11;
+    public static int OP_CUSTOM0 = 0b00_010_11;
 
     //I_type opcode: 0010 0011
     public static int I_TYPE = 0x13;
@@ -158,9 +157,6 @@ public class riscv extends Machine {
         assert opcode >= 0 && rd >=0 && func3 >=0 && rs1 >=0 && imm12 >= 0; // Zero-extend by caller
         return  (imm12 << 20) | (rs1 << 15) | (func3 << 12) | (rd << 7) | opcode;
     }
-    //public static int i_type(int opcode, int rd, int func3, int rs1, int imm12) {
-    //    return i_type(opcode,rd,func3,rs1,imm,0);
-    //}
 
 
     // S-type instructions(store)