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authorCliff Click <cliffc@acm.org>2025-03-28 15:58:58 -0700
committerCliff Click <cliffc@acm.org>2025-03-28 15:58:58 -0700
commit82b4b2187d51f96f3217b10febfbf18071ec61fc (patch)
treecfc639ed9386baab7dab02d4456467d5e8c318a0 /chapter21/src/main/java/com
parentb3c108731794fed83015ba92a651af13a3a1477d (diff)
downloadSimple-82b4b2187d51f96f3217b10febfbf18071ec61fc.tar.gz
Simple-82b4b2187d51f96f3217b10febfbf18071ec61fc.zip
risc5 encoding bug
Diffstat (limited to 'chapter21/src/main/java/com')
-rw-r--r--chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AUIPC.java2
-rw-r--r--chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LUI.java2
-rw-r--r--chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java11
3 files changed, 10 insertions, 5 deletions
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AUIPC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AUIPC.java
index 59075190..8563a010 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AUIPC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AUIPC.java
@@ -17,7 +17,7 @@ public class AUIPC extends ConstantNode implements MachNode, RIPRelSize {
@Override public void encoding( Encoding enc ) {
enc.relo(this);
short dst = enc.reg(this);
- enc.add4(riscv.u_type(0x17, dst, 0));
+ enc.add4(riscv.u_type(riscv.OP_AUIPC, dst, 0));
}
// Delta is from opcode start, but X86 measures from the end of the 5-byte encoding
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LUI.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LUI.java
index 343343e0..75ad6496 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LUI.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LUI.java
@@ -21,7 +21,7 @@ public class LUI extends ConstantNode implements MachNode {
long x = ((TypeInteger)_con).value();
int imm20 = (int)(x>>12) & 0xFFFFF;
short dst = enc.reg(this);
- int lui = riscv.u_type(0x17, dst, imm20);
+ int lui = riscv.u_type(riscv.OP_LUI, dst, imm20);
enc.add4(lui);
}
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index 7baef360..1695d8fe 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -103,13 +103,18 @@ public class riscv extends Machine {
};
//
// major opcode: OP
- public static int OP = 0b01_100_11;
- public static int OP_FP = 0b10_100_11;
public static int OP_CUSTOM0 = 0b00_010_11;
+ public static int OP_AUIPC = 0b00_101_11;
+
public static int OP_CUSTOM1 = 0b01_010_11;
+ public static int OP = 0b01_100_11;
+ public static int OP_LUI = 0b01_101_11;
+
public static int OP_CUSTOM2 = 0b10_010_11;
- public static int OP_RESERVED= 0b11_010_11;
+ public static int OP_FP = 0b10_100_11;
+
public static int OP_BRANCH = 0b11_000_11;
+ public static int OP_RESERVED= 0b11_010_11;
//I_type opcode: 0010 0011
public static int I_TYPE = 0x13;