Ch20 encoding (#176)

* Update README.md

* Update ListScheduler.java

* command line launcher for simple

Parser bug fref in args
Some new test cases.

* Add basic RegMask for more than 64 bits of register mask.

Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension

* ASM Printer

InstSel handles folding 2+ ideal ops into 1 machine op

* handle instSel for some control flow

Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.

* Basic if-block inst selects and asm prints

* Add mul-by-coinstant to shift

* left shift codegen basic

* exclude RSP from *write* mask

* 2-arg add (not immediate)

mul-by-small constant opt.  Some utilities.

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* inst select for new struct allocation

* Float, bitwise and arithmetic operands codegen x86-64 (#150)

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* float ops without imm values

* merge

* merge

* inst select for new struct allocation

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* float ops without imm values

* merge

* merge

* Rebased on ch 19

* Update tests

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* cleanup after merge

alpha-sort helper fcns
implicit test vs zero/null

* Add LEA op

asm print works on ideal nodes for all tests

* Minor cleanup lea

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* x86 addressing modes during inst select

Drop New taking inits; just follow with initializing stores.  Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate

* call setup

* extended ch13, 14,15,16 (#153)

* merge2

* merge3

* Fix a few minor fuzzer bugs

* Force array layout

ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.

* Fix a bunch of float issues

was deleting required inputs

* simpler invariant

defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).

* Call & CallR X86 instructions

* merge2

* Add-from-memory op

Remove FP immediate forms.

* Remove name from TFP

Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

* New (#154)

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* call setup

* merge2

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Add CmpMem form

Common addressing mode print
LEA can skip a base

* Add a AddFMemX86

A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.

* Docs

* XMM reg mask fix

Minor README updates

* Allow inverted cmp/mem

narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info

* Support "*ptr op= val"

at least for MemAdd

* missed golden rule update

* Array len is u32

load-after-store zero/sign-extends if the store is truncating

* One more missed case

* READMEs

* Update README.md

* Update README.md

* Move printing into print dir

* Move codegen into codegen

* Framework for Reg Alloc

* riscv init

* added not imm form bitwise shifts and ops plus test cases

* addressing modes(high chance it'll get deleted)

* First cut BuildLRG

RegMask.EMPTY -> null

* fix minor bug

* Setup for first simple split

* First cut split code for mismatch regs

* delete non existing matches

* replace RegMask.Empty with null

* Live Ranges U-F

BuildLRG for Phi
Add CmpFX86

* FPR return

CallEndX86 needed to tell fp return from gpr ret
Call has no output regs.

* riscv handle store and load, fltRisch uses risc reg now

* load float into GPR and then later in RA do hard split.

* minor changes

* Next cut regalloc

Building IFG.
Coloring.
Some nested spilling
Optimize divf/con -> mul times inverse

* turn off ch20 tests

* Update Chapter20Test.java

* RISC-V basic isel (#156)

* Initial push

Major CodeGen cleanup; most static globals move into the CodeGen object.

* Minor progress bug with mutual recursion

* Add test from pr#148

* First cut x86 "port"

Only "return 0;", no registers, no encoding, but yah gotta start somewhere

* Update README.md

* Update README.md

* Update ListScheduler.java

* command line launcher for simple

Parser bug fref in args
Some new test cases.

* Add basic RegMask for more than 64 bits of register mask.

Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension

* ASM Printer

InstSel handles folding 2+ ideal ops into 1 machine op

* handle instSel for some control flow

Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.

* Basic if-block inst selects and asm prints

* Add mul-by-coinstant to shift

* left shift codegen basic

* exclude RSP from *write* mask

* 2-arg add (not immediate)

mul-by-small constant opt.  Some utilities.

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* inst select for new struct allocation

* Float, bitwise and arithmetic operands codegen x86-64 (#150)

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* float ops without imm values

* merge

* merge

* inst select for new struct allocation

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* float ops without imm values

* merge

* merge

* Rebased on ch 19

* Update tests

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* cleanup after merge

alpha-sort helper fcns
implicit test vs zero/null

* Add LEA op

asm print works on ideal nodes for all tests

* Minor cleanup lea

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* x86 addressing modes during inst select

Drop New taking inits; just follow with initializing stores.  Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate

* call setup

* extended ch13, 14,15,16 (#153)

* merge2

* merge3

* Fix a few minor fuzzer bugs

* Force array layout

ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.

* Fix a bunch of float issues

was deleting required inputs

* simpler invariant

defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).

* Call & CallR X86 instructions

* merge2

* Add-from-memory op

Remove FP immediate forms.

* Remove name from TFP

Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

* New (#154)

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* call setup

* merge2

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Add CmpMem form

Common addressing mode print
LEA can skip a base

* Add a AddFMemX86

A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.

* Docs

* XMM reg mask fix

Minor README updates

* Allow inverted cmp/mem

narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info

* Support "*ptr op= val"

at least for MemAdd

* missed golden rule update

* Array len is u32

load-after-store zero/sign-extends if the store is truncating

* One more missed case

* riscv init

* added not imm form bitwise shifts and ops plus test cases

* addressing modes(high chance it'll get deleted)

* fix minor bug

* delete non existing matches

* replace RegMask.Empty with null

* riscv handle store and load, fltRisch uses risc reg now

* load float into GPR and then later in RA do hard split.

* minor changes

* turn off ch20 tests

* Update Chapter20Test.java

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Bring pr/154 to ch 20

RISC5 changes.
Some missing x86 ops.
Still needs some calling convention love.

* First cut regalloc working

Biased coloring; tracking splits around a LRG.
Separate split for self-conflicts.
postColor to remove junk splits.
Some minor riscv fixes.

* Compile some riscv codes

If SplitEmptyMask does not apply, fall back to normal split.
Missing CmpFRISC.
Renamed riscv flags.
RetRISC handls FPR
remove extra RegMask constructurs

* add riscv port to readme

* arm init

* Progress reg alloc

Handle multi-node projections.
A little smarter about 2-addr scheduling
RegAlloc must-have single registers removes from other masks instead of interfering; had the mask removal backwards in a few cases.
LRG/RegMask COW expand masks before mutating.
Clone small constants instead of spilling.
Alloc & ProjX86 get output reg masks.
Full print large reg masks with sp+offset

* UF LRGs can be null during coloring

* Finish UF find

* work in progress

* README updates

* Fix ch19 mis-merge?

* x86 call args, risc5 load/store regs

* arm2 bs

* Push RISC WMASK

avoid writing to RSP

* work in progress

* clearnup arm

* Progress calling convention allocations

Call unlinks before reg alloc.
CallEnd tracks RPC
CallX86 requires TFP for correct ABI
Bias Color tracks 2-addr.
RPC gets a mask/stack-slot
Clean up call/fun ABI
Fix mask RET, RET_F
Fix print stack slot
Remove isMultiHead, isMultiTail
Better all-asm print

* Beef up Newton test

* fixed main pr problems

* regmask extra comments

* Clean pass normal tests

New fcn print upgrades several golden rule tests.
Move the unlink-all from the walk::err call (which IS used during IterPeeps) to GCM.
CallEnd upgrades return type based on constant call.
Fix unlink to also unlink CallEnd
Constant TFP print checks constant
Tested an untested Load

* Arm basics, minor changes in riscv (#160)

* Initial push

Major CodeGen cleanup; most static globals move into the CodeGen object.

* Minor progress bug with mutual recursion

* Add test from pr#148

* First cut x86 "port"

Only "return 0;", no registers, no encoding, but yah gotta start somewhere

* Update README.md

* Update README.md

* Update ListScheduler.java

* command line launcher for simple

Parser bug fref in args
Some new test cases.

* Add basic RegMask for more than 64 bits of register mask.

Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension

* ASM Printer

InstSel handles folding 2+ ideal ops into 1 machine op

* handle instSel for some control flow

Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.

* Basic if-block inst selects and asm prints

* Add mul-by-coinstant to shift

* left shift codegen basic

* exclude RSP from *write* mask

* 2-arg add (not immediate)

mul-by-small constant opt.  Some utilities.

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* inst select for new struct allocation

* Float, bitwise and arithmetic operands codegen x86-64 (#150)

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* float ops without imm values

* merge

* merge

* inst select for new struct allocation

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* float ops without imm values

* merge

* merge

* Rebased on ch 19

* Update tests

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* cleanup after merge

alpha-sort helper fcns
implicit test vs zero/null

* Add LEA op

asm print works on ideal nodes for all tests

* Minor cleanup lea

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* x86 addressing modes during inst select

Drop New taking inits; just follow with initializing stores.  Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate

* call setup

* extended ch13, 14,15,16 (#153)

* merge2

* merge3

* Fix a few minor fuzzer bugs

* Force array layout

ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.

* Fix a bunch of float issues

was deleting required inputs

* simpler invariant

defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).

* Call & CallR X86 instructions

* merge2

* Add-from-memory op

Remove FP immediate forms.

* Remove name from TFP

Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

* New (#154)

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* call setup

* merge2

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Add CmpMem form

Common addressing mode print
LEA can skip a base

* Add a AddFMemX86

A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.

* Docs

* XMM reg mask fix

Minor README updates

* Allow inverted cmp/mem

narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info

* Support "*ptr op= val"

at least for MemAdd

* missed golden rule update

* Array len is u32

load-after-store zero/sign-extends if the store is truncating

* One more missed case

* riscv init

* added not imm form bitwise shifts and ops plus test cases

* addressing modes(high chance it'll get deleted)

* fix minor bug

* delete non existing matches

* replace RegMask.Empty with null

* riscv handle store and load, fltRisch uses risc reg now

* load float into GPR and then later in RA do hard split.

* minor changes

* turn off ch20 tests

* Update Chapter20Test.java

* add riscv port to readme

* arm init

* work in progress

* arm2 bs

* work in progress

* clearnup arm

* fixed main pr problems

* regmask extra comments

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Update Chapter20Test.java

* Weaken range-check test

since no range checks... test cannot fail (pass)

* Fix issue #161

Error adding 'null' and '5'

* bug fixs, cloning constants

Fix bug missing Find.
Fix bug setDef does unordered removal from basic blocks.
Use cloned constants for spilling.

* RA fixes

SplitSelfConflict MUST split before uses and after defs.
Split global constants across functions
Missing find in union;
Inserting split after new inserted wrong place
Pre-remove null LRGs before color.
Bias color hunts through Phis
Shorten InstructionSelection.
Rename !unified() to leader()
AddMemX86 is 2-addr
Add CastXXX to preserve register across cast.

* encoding init

* encoding init 2

* rex fix

* indirect addressing modes

* setop change opcode, rename FLOAT_OFFSET

* mask sib and modrm with 3 bits, 4th bit goes into rex.

* sign extend div with cqo

* idiv input is fixed to rax and RMASK, grab input from second slot when encoding

* encoding of newx86

* tfp and CallEndNode encoding

* sib improvement

* more cleanups

* more cleanups

* Allow a killMap to kill regs.

Bugfix scheduler.
Bugfix spiller - self-conflict order depended on hashtable iteration order, which depended on System.hashCode which would vary run to run.
Improvements to coloring
Improvements to spill quality testing

* Added flags-kill for XOR

* Missing add-deps from fuzzer

* Update Chapter14Test.java

* fixed order of operands

* base rex fixup

* more bug fix

* remove jukn files

* minimal "make release"

* further fixes

* minor fixes

* minor fixes

* minor fixes

* base != -1 check, precedence fix

* Add regkills in IFG building

Fix bug LRG union stats
Adjust self-conflict splits to be slightly less aggressive
In every use-side split, dont split-after-split same block.
NewNode is a multi, does not define a register

* 64 bit encoding for gpr(s) load

* RA improvements

Attempt to commute to keep reg-masks compatible.
Clones with kills (x86 XOR killing flags to zero) fail before the flag-def.
Bugfix failed to color last lrg.
More smarts on picking trivial LRGs during coloring
Drop isSplit, add SplitNode
Pass regalloc round to all splits for debugging
Self-conflict no split on loop backedge.
Handle split that gets made goes dead
No-reg-mask spilling handles case with many def/uses.
Add DivIX86
BrainFuck, MergeSort now allocate as testing

* 8 bit imm support

* conditional jump fix

* Push l,ast change, unbreak branch

* XOR remove extra opcode, imm size supports 8 bit.

* Finally pass the `new [u8]` double-copy test

* Fix several ARM reg setup problems

Finish Split bypass check
ARM: rsp is also a fixed zero, in R31.  R0 is a valid register.
CallArm prints args, passes TFP for arg selection.  Does not return a register.  All CallEndARM which DOES return a register.  Parms missing tfp for float args.  ProjARM after a New missing regs.  RetARM missing RPC.
Remove hopeful DivIX86

* 64 bit imm for alu ops encoded in extra reg then use it in Op as an operand

* Bunch of minor arm, risc fixes

small constants not cloning

* jump invert encoding

* warning comment

* Much ARM fixage

One More Go-Round with Better Biased Colors
Fix bug picking deepest spills to bias.
ARM: remove default 2-address.  Fix regmask overflow.  Rename some ops to be canonical.

* Fixes to release

Port does not have to be in a Simple named directory.
Call convention is just a string, no enum
Missed some tests running RISC, ARM.

* Minor release change to allow another foreign port

* better split encoding and fix CallInMask

* notNode

* fix callInMask

* riscv init

* riscv basic ALU ops and types of instructions

* Allowing non-Simple repo ports

Expanding public API slightly so alternative (non-Simple repo) ports can happen.
RegMask supports single-bit-set and a long bitmask.
Bugfix GCM splitting multiple global constants.
Bugfix LCM grabbing a projection vs multi
Bugfix RegAlloc when avoiding splitting a clonable
Source code in release
More timing in CodeGen

* riscv indirect addressing and function calls

* Cleanup call ABI presentation

Everybody uses the same names, same code shapes

* Caller save regs

...not callee save yet

* Expose caller save regs

* Store Risc adjustments, no imm in MemOpRISC

* specific print encoding for cpus

* merge fixup

* More x86,risc,arm call convention fixes

Collect callee and caller save masks (inverts of each other, except for spills).
Reorg layout to be closer to each other; remove dead mask definitions; add final keyword

* lui fix up with 32 bit immediates

* Callee-save registers

Callee-save registers and masks and inserting LRGs for same and spilling and picking good spills.  Insert CalleeSaveNodes and edges to RetXXXs and RegMasks for those edges.
Iterators for regmask.
Better printing post-allocation

* RegMask supports 128 bits

All regs available arm, risc.
MergeSort compiles & runs

* added flags splitting

* Fix risc5 compares

No flags on risc5.
Branch takes 2 inputs (one can be imm12).
Float compare only sets a GPR to 0/1.
Bool has a isFloat
Common risc5 imm-form handling

* extend test cases

* imm encoding, flags fixed

* grep for Todo: relocs

* float riscv fixed

* flags for set

* lui fix for small bits [0, 12]

* arm init

* arm last touches

* fmov still needs fix

* minor fixes

* minor fixes(2)

* got rid of unnecessary stuff

* create ch21

* remove encodings from chapter20 dir

* 1/2 pass cleaning up ARM encoding API

* ARM encoding compiles

* Risc R_TYPE and I_TYPE

* Progress RISC encodings

Missing lots of stuff still

* progress risc encoding

* risc encodings compile

* Update README.md

* Fold up redundant OP/OP-FP risc5 encoding

* x86 mem opcodes first cut

break out MemOp encodings into parts; change x86 indirectAdr to use Encoding class, remove redundant asserts & code

* x86 mem op encodings

* x86 reg+imm forms

* most reg-reg forms

* More x86 encodings

* Last few encodings

* switch to binary literals over decimals for opcodes

* logical immediates fixed, bitwise ops imm forms

* tfp and setArm fixed

* PC relative float for riscv

* readme init

* Merged pr/169

* Fixed the array1 test encodings

Clean up branch invert logic during BB layout
Cleanup branch target printing for RISC,ARM
ImmRISC ops mask imm12 to 12 bits
Fix NewRISC; hardcode RPC as part of call
Fix RISC inverting branchs >,>=

* floatarm encoding

* tfparm and intarm

* uncontional jump encoding for arm and riscv

* smarter IntARM, Intx86 does not always include rex.

* REX after PREFIX

* fixup load and store indirect

* updated rex prefix, if its 0x40 then its not needed

* Rex fix for floats, got rid of unnecessary stuff.

* rename to camel case, better param name

* add test export

* merged

* store opt

* store and load optimised forms handled

* tfp patch

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

8 files changed, 139 insertions, 11 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/codegen/Encoding.java b/chapter21/src/main/java/com/seaofnodes/simple/codegen/Encoding.java
index 67eeb3c2..0162bc84 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/codegen/Encoding.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/codegen/Encoding.java
@@ -53,6 +53,10 @@ public class Encoding {
 
     public Encoding add1( int op ) { _bits.write(op); return this; }
 
+    public void add2( int op ) {
+        _bits.write(op    );
+        _bits.write(op>> 8);
+    }
     // Little endian write of a 32b opcode
     public void add4( int op ) {
         _bits.write(op    );
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java
index 0ba47317..f42dae75 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java
@@ -4,9 +4,10 @@ import com.seaofnodes.simple.*;
 import com.seaofnodes.simple.codegen.*;
 import com.seaofnodes.simple.node.ConstantNode;
 import com.seaofnodes.simple.node.MachNode;
+import com.seaofnodes.simple.node.cpus.riscv.riscv;
 import com.seaofnodes.simple.type.TypeFunPtr;
 
-public class TFPARM extends ConstantNode implements MachNode {
+public class TFPARM extends ConstantNode implements MachNode, RIPRelSize {
     TFPARM( ConstantNode con ) { super(con); }
     @Override public String op() { return "ldx"; }
     @Override public RegMask regmap(int i) { return null; }
@@ -22,6 +23,28 @@ public class TFPARM extends ConstantNode implements MachNode {
         arm.imm_inst(enc,this,0b1001000100,0);
         enc.add4(adrp);
     }
+
+    @Override public byte encSize(int delta) {
+        if( -(1L<<12) <= delta && delta < (1L<<12) ) return 4;
+        throw Utils.TODO();
+    }
+
+    // Delta is from opcode start
+    @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) {
+        short rpc = enc.reg(this);
+        if(opLen ==4 ) {
+            // opstart of add
+            int next = opStart + opLen;
+            int adrp_delta = delta >> 12;
+            // patch upper 20 bits via adrp
+            enc.patch4(opStart, arm.adrp(1, adrp_delta & 0b11, 0b10000, adrp_delta >> 2, rpc));
+            // low 12 bits via add
+            enc.patch4(next, arm.imm_inst_l(enc, this, 0b1001000100, delta & 0xfff));
+        } else {
+            throw Utils.TODO();
+        }
+    }
+
     @Override public void asm(CodeGen code, SB sb) {
         String reg = code.reg(this);
         _con.print(sb.p(reg).p(" #"));
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
index b35f600a..4b0781f2 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
@@ -224,6 +224,13 @@ public class arm extends Machine {
         enc.add4(body);
     }
 
+    public static int imm_inst_l(Encoding enc, Node n, int opcode, int imm12) {
+        short self = enc.reg(n);
+        short reg1 = enc.reg(n.in(1));
+        int body = imm_inst(opcode, imm12&0xFFF, reg1, self);
+        return body;
+    }
+
     // for normal add, reg1, reg2 cases (reg-to-reg)
     // using shifted-reg form
     public static int r_reg(int opcode, int shift, int rm, int imm6, int rn, int rd) {
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java
index 873a07ce..6cb219df 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java
@@ -6,7 +6,7 @@ import com.seaofnodes.simple.node.ConstantNode;
 import com.seaofnodes.simple.node.MachNode;
 import com.seaofnodes.simple.type.TypeFunPtr;
 
-public class TFPRISC extends ConstantNode implements MachNode {
+public class TFPRISC extends ConstantNode implements MachNode, RIPRelSize {
     TFPRISC(ConstantNode con) { super(con); }
     @Override public String op() { return "ldx"; }
     @Override public RegMask regmap(int i) { return null; }
@@ -26,6 +26,27 @@ public class TFPRISC extends ConstantNode implements MachNode {
         enc.add4(addi);
     }
 
+    @Override public byte encSize(int delta) {
+        if( -(1L<<11) <= delta && delta < (1L<<11) ) return 4;
+        throw Utils.TODO();
+    }
+
+    // Delta is from opcode start
+    @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) {
+        short rpc = enc.reg(this);
+        if( opLen==4 ) {
+            // AUIPC (upper 20 bits)
+            // opstart of add
+            int next = opStart + opLen;
+            enc.patch4(opStart,riscv.u_type(0b0010111, rpc, delta));
+            // addi(low 12 bits)
+            enc.patch4(next,riscv.i_type(0b0010011, rpc, 0, rpc, delta & 0xFFF));
+            // addi
+        } else {
+            throw Utils.TODO();
+        }
+    }
+
     @Override public void asm(CodeGen code, SB sb) {
         _con.print(sb.p(code.reg(this)).p(" #"));
     }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/LoadX86.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/LoadX86.java
index 39525ed1..6dd3e3dc 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/LoadX86.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/LoadX86.java
@@ -4,6 +4,8 @@ import com.seaofnodes.simple.SB;
 import com.seaofnodes.simple.codegen.*;
 import com.seaofnodes.simple.node.LoadNode;
 import com.seaofnodes.simple.node.Node;
+import com.seaofnodes.simple.type.Type;
+import com.seaofnodes.simple.type.TypeInteger;
 
 public class LoadX86 extends MemOpX86 {
     LoadX86( LoadNode ld, Node base, Node idx, int off, int scale ) {
@@ -13,11 +15,42 @@ public class LoadX86 extends MemOpX86 {
     @Override public RegMask outregmap() { return x86_64_v2.MEM_MASK; }
     @Override public void encoding( Encoding enc ) {
         // REX.W + 8B /r	MOV r64, r/m64
+        // Zero extension for u8, u16 and u32 but sign extension i8, i16, i32
+        // Use movsx and movzx
+
         short dst = enc.reg(this );
         short ptr = enc.reg(ptr());
         short idx = enc.reg(idx());
-        enc.add1(x86_64_v2.rex(dst, ptr, idx));
-        enc.add1(0x8B); // opcode
+        if (_declaredType != TypeInteger.U32) {
+            enc.add1(x86_64_v2.rex(dst, ptr, idx));
+        }
+
+        if(_declaredType == TypeInteger.I8) {
+            // sign extend: REX.W + 0F BE /r	MOVSX r64, r/m8
+            enc.add1(0x0F);
+            enc.add1(0xBE);
+        } else if(_declaredType == TypeInteger.I16) {
+            // sign extend: REX.W + 0F BF /r	MOVSX r64, r/m16
+            enc.add1(0x0F);
+            enc.add1(0xBF);
+        } else if(_declaredType == TypeInteger.I32) {
+            // sign extend: REX.W + 63 /r	MOVSXD r64, r/m32
+            enc.add1(0x63);
+        } else if(_declaredType == TypeInteger.U8) {
+            // zero extend: REX.W + 0F B6 /r	MOVZX r64, r/m8
+            enc.add1(0x0F);
+            enc.add1(0xB6);
+        } else if(_declaredType == TypeInteger.U16) {
+            // zero extend:   REX.W + 0F B7 /r	MOVZX r64, r/m16
+            enc.add1(0x0F);
+            enc.add1(0xB7);
+        } else if(_declaredType == TypeInteger.U32) {
+            // zero extend:   8B /r	MOV r32, r/m32
+            enc.add1(0x8B);
+        } else if(_declaredType == TypeInteger.BOT) {
+            // REX.W + 8B /r    MOV r64, r/m64
+            enc.add1(0x8B);
+        }
 
         // includes modrm internally
         x86_64_v2.indirectAdr(_scale, idx, ptr, _off, dst, enc);
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/StoreX86.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/StoreX86.java
index 4a54663d..8c2e0612 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/StoreX86.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/StoreX86.java
@@ -2,6 +2,7 @@ package com.seaofnodes.simple.node.cpus.x86_64_v2;
 
 import com.seaofnodes.simple.SB;
 import com.seaofnodes.simple.codegen.*;
+import com.seaofnodes.simple.node.ConstantNode;
 import com.seaofnodes.simple.node.Node;
 import com.seaofnodes.simple.node.StoreNode;
 import java.util.BitSet;
@@ -27,13 +28,27 @@ public class StoreX86 extends MemOpX86 {
         short idx = enc.reg(idx());
         short src = enc.reg(val());
 
-        enc.add1(x86_64_v2.rex(src, ptr, idx));
+        int imm_op = x86_64_v2.selectOpcodeForImmStore(_imm);
+        if(src == -1 && _imm != 0) {
+            if(imm_op == -1)         {enc.add1(x86_64_v2.rex(src, ptr, idx));enc.add1(0xC7); }
+            else enc.add1(imm_op);
+        } else {
 
-        // switch on opcode depending on instruction
-        enc.add1( src == -1 ? 0xC7 : 0x89 );
+            if(_declaredType.log_size() == 0) enc.add1(0x88);
+            if(_declaredType.log_size() == 1) enc.add1(0x89);
+            if(_declaredType.log_size() == 2) enc.add1(0x89);
+            if(_declaredType.log_size() == 3) {enc.add1(x86_64_v2.rex(src, ptr, idx)); enc.add1(0x89);}
+        }
 
         x86_64_v2.indirectAdr(_scale, idx, ptr, _off, src, enc);
-        if( src == -1 ) enc.add4(_imm);
+        if( src == -1 ) {
+            switch (x86_64_v2.imm_size(_imm)) {
+                case 8: enc.add1(_imm); break;
+                case 16: enc.add2(_imm); break;
+                case 32: enc.add4(_imm); break;
+                case 64: enc.add8(_imm); break;
+            }
+        }
     }
 
     // General form: "stN  [base + idx<<2 + 12],val"
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/TFPX86.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/TFPX86.java
index 13b9f8a3..be4d1a83 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/TFPX86.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/TFPX86.java
@@ -3,11 +3,12 @@ package com.seaofnodes.simple.node.cpus.x86_64_v2;
 import com.seaofnodes.simple.*;
 import com.seaofnodes.simple.codegen.*;
 import com.seaofnodes.simple.node.*;
+import com.seaofnodes.simple.node.cpus.riscv.riscv;
 import com.seaofnodes.simple.type.Type;
 import com.seaofnodes.simple.type.TypeFunPtr;
 
 // Function constants
-public class TFPX86 extends ConstantNode implements MachNode {
+public class TFPX86 extends ConstantNode implements MachNode, RIPRelSize {
     TFPX86( ConstantNode con ) {  super(con); }
     @Override public String op() {
         return _con == Type.NIL ? "xor" : "ldx";
@@ -42,6 +43,15 @@ public class TFPX86 extends ConstantNode implements MachNode {
         enc.add4(0);
     }
 
+    @Override public byte encSize(int delta) {
+        return 7;
+    }
+
+    // Delta is from opcode start
+    @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) {
+        enc.patch4(opStart + 3, delta - 7);
+    }
+
     // Human-readable form appended to the SB.  Things like the encoding,
     // indentation, leading address or block labels not printed here.
     // Just something like "ld4\tR17=[R18+12] // Load array base".
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java
index 9d7b1a26..1d30bc4b 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java
@@ -109,6 +109,20 @@ public class x86_64_v2 extends Machine {
         if( 8 <= idx && idx <= 15 ) rex |= 0b00000010; // REX.X
         return rex;
     }
+    // return opcode for optimised immediate store
+    public static int selectOpcodeForImmStore(long imm) {
+        if(imm8(imm)) return 0xC6;
+        if(imm16(imm)) return 0xC7;
+        if(imm32(imm)) return 0xC7;
+        return -1;
+    }
+    // return the size of the immediate
+    public static int imm_size(long imm) {
+        if(imm8(imm)) return 8;
+        if(imm16(imm)) return 16;
+        if(imm32(imm)) return 32;
+        return 64;
+    }
 
     public static int rex(int reg, int ptr, int idx) {
         return rex(reg, ptr, idx, true);
@@ -410,16 +424,17 @@ public class x86_64_v2 extends Machine {
     }
 
     public static boolean imm8( long imm ) { return -128 <= imm && imm <= 127; }
+    public static boolean imm16(long imm) {return -32768 <= imm && imm <= 32767; }
     public static boolean imm32( long imm ) { return (int)imm==imm; }
 
     // Attempt a full LEA-style break down.
     private Node add(AddNode add) {
         Node lhs = add.in(1);
         Node rhs = add.in(2);
-        if( lhs instanceof LoadNode ld && ld.nOuts() == 1 )
+        if( lhs instanceof LoadNode ld && ld.nOuts() == 1 && ld._declaredType.log_size() >= 3)
             return new AddMemX86(add, address(ld), ld.ptr(), idx, off, scale, imm(rhs), val);
 
-        if(rhs instanceof LoadNode ld && ld.nOuts() == 1)
+        if(rhs instanceof LoadNode ld && ld.nOuts() == 1 && ld._declaredType.log_size() >= 3)
             throw Utils.TODO(); // Swap load sides
 
         // Attempt a full LEA-style break down.