bugz

Fix RA bug using Win64 and not full spilling in a single block.
riscv/arm demand SystemV calling convention
Cleanup ch21 tests; add 1 export test

5 files changed, 20 insertions, 5 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java b/chapter21/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java
index c6ac68c4..88144a1d 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java
@@ -192,7 +192,7 @@ public class CodeGen {
         // Look for CPU in fixed named place:
         //   com.seaofnodes.simple.node.cpus."cpu"."cpu.class"
         String clzFile = base+"."+cpu+"."+cpu;
-        try { _mach = ((Class<Machine>) Class.forName( clzFile )).getDeclaredConstructor().newInstance(); }
+        try { _mach = ((Class<Machine>) Class.forName( clzFile )).getDeclaredConstructor(new Class[]{CodeGen.class}).newInstance(this); }
         catch( Exception e ) { throw new RuntimeException(e); }
 
         // Convert to machine ops
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegAlloc.java b/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegAlloc.java
index 68b9cdcc..4b3557cd 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegAlloc.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/codegen/RegAlloc.java
@@ -149,7 +149,8 @@ public class RegAlloc {
         byte round=0;
         while( !graphColor(round) ) {
             split(round);
-            assert round < 7; // Really expect to be done soon
+            if( round >= 7 )    // Really expect to be done soon
+                throw Utils.TODO("Allocator taking too long");
             round++;
         }
         postColor();                       // Remove no-op spills
@@ -238,7 +239,7 @@ public class RegAlloc {
             makeSplit("def/empty1",round,lrg).insertAfter((Node)lrg._machDef, false/*true*/);
         // Split just before use
         if( lrg._1regUseCnt==1 )
-            insertBefore((Node)lrg._machUse,lrg._uidx,"use/empty1",round,lrg);
+            insertBefore((Node)lrg._machUse,lrg._uidx,"use/empty1",round,lrg,false);
         return true;
     }
 
@@ -421,7 +422,7 @@ public class RegAlloc {
         for( Node n : _ns ) assert !n.isDead();
     }
 
-    void insertBefore(Node n, int i, String kind, byte round, LRG lrg) {
+    void insertBefore(Node n, int i, String kind, byte round, LRG lrg, boolean skip) {
         Node def = n.in(i);
         // Effective block for use
         CFGNode cfg = n instanceof PhiNode phi ? phi.region().cfg(i) : n.cfg0();
@@ -435,9 +436,12 @@ public class RegAlloc {
         }
         makeSplit(def,kind,round,lrg).insertBefore(n, i);
         // Skip split-of-split same block
-        if( def instanceof SplitNode && cfg==def.cfg0() )
+        if( skip && def instanceof SplitNode && cfg==def.cfg0() )
             n.in(i).setDefOrdered(1,def.in(1));
     }
+    void insertBefore(Node n, int i, String kind, byte round, LRG lrg) {
+        insertBefore(n,i,kind,round,lrg,true);
+    }
 
     private Node makeSplit( Node def, String kind, byte round, LRG lrg ) {
         Node split = def instanceof MachNode mach && mach.isClone()
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
index d2f50e45..92638562 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java
@@ -7,6 +7,10 @@ import com.seaofnodes.simple.type.*;
 import java.io.ByteArrayOutputStream;
 
 public class arm extends Machine {
+    public arm( CodeGen code ) {
+        if( !"SystemV".equals(code._callingConv) )
+            throw new IllegalArgumentException("Unknown calling convention "+code._callingConv);
+    }
 
     // ARM64
     @Override public String name() { return "arm"; }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index 285b4583..dceef330 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -8,6 +8,12 @@ import com.seaofnodes.simple.type.*;
 import java.io.ByteArrayOutputStream;
 
 public class riscv extends Machine {
+
+    public riscv(CodeGen code) {
+        if( !"SystemV".equals(code._callingConv) )
+            throw new IllegalArgumentException("Unknown calling convention "+code._callingConv);
+    }
+
     @Override public String name() {return "riscv";}
 
     // Using ABI names instead of register names
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java
index 20abb4e8..ff045ef8 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/x86_64_v2.java
@@ -8,6 +8,7 @@ import com.seaofnodes.simple.type.*;
 import java.io.ByteArrayOutputStream;
 
 public class x86_64_v2 extends Machine {
+    public x86_64_v2( CodeGen code ) {}
     // X86-64 V2.  Includes e.g. SSE4.2 and POPCNT.
     @Override public String name() { return "x86_64_v2"; }
     @Override public int defaultOpSize() { return 5; }