Add 32b risc5 emulator

2 files changed, 8 insertions, 7 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java
index 3fa6862a..7babe04c 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java
@@ -26,11 +26,12 @@ public class FunRISC extends FunNode implements MachNode {
         // Stack frame size: _maxSlot - max(arg), padded to 16.
         _maxArgSlot = riscv.maxSlot(enc._fun.sig());
         _frameAdjust = (short) (_maxSlot+1 - _maxArgSlot);
-        if( _frameAdjust == 0 ) return; // Skip if no frame adjust
-        enc.add4(riscv.i_type(riscv.OP_IMM, riscv.SP, 0, riscv.SP, (_frameAdjust*8) & 0xFFF));
+        if( _frameAdjust != 0 )
+            enc.add4(riscv.i_type(riscv.OP_IMM, riscv.SP, 0, riscv.SP, (_frameAdjust*-8) & 0xFFF));
     }
 
     @Override public void asm(CodeGen code, SB sb) {
-        sb.p("rsp += #").p(_frameAdjust*8);
+        if( _frameAdjust != 0 )
+            sb.p("rsp += #").p(_frameAdjust*-8);
     }
 }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
index aa1d99e9..2edc61c7 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
@@ -26,16 +26,16 @@ public class RetRISC extends ReturnNode implements MachNode {
     @Override public RegMask outregmap() { return null; }
     @Override public void encoding( Encoding enc ) {
         int frameAdjust = fun()._frameAdjust;
-        if( frameAdjust > 0 )
-            enc.add4(riscv.i_type(riscv.OP_IMM, riscv.SP, 0, riscv.SP, (frameAdjust*-8) & 0xFFF));
+        if( frameAdjust != 0 )
+            enc.add4(riscv.i_type(riscv.OP_IMM, riscv.SP, 0, riscv.SP, (frameAdjust*8) & 0xFFF));
         short rpc = enc.reg(rpc());
         enc.add4(riscv.i_type(riscv.OP_JALR, riscv.ZERO, 0, rpc, 0));
     }
 
     @Override public void asm(CodeGen code, SB sb) {
         int frameAdjust = fun()._frameAdjust;
-        if( frameAdjust>0 )
-            sb.p("rsp += #").p(frameAdjust*-8).p("\nret");
+        if( frameAdjust!=0 )
+            sb.p("rsp += #").p(frameAdjust*8).p("\nret");
         // Post code-gen, just print the "ret"
         if( code._phase.ordinal() <= CodeGen.Phase.RegAlloc.ordinal() )
             // Prints return reg (either A0 or FA0), RPC (always R1) and then