Fix risc5 branch invert

Had conditions on forced invert mixed up.
Sometimes need both a negate and a swap.
rename invert as negate.

2 files changed, 18 insertions, 11 deletions

diff --git a/chapter21/src/test/java/com/seaofnodes/simple/Chapter21Test.java b/chapter21/src/test/java/com/seaofnodes/simple/Chapter21Test.java
index 9d99c01c..2e071531 100644
--- a/chapter21/src/test/java/com/seaofnodes/simple/Chapter21Test.java
+++ b/chapter21/src/test/java/com/seaofnodes/simple/Chapter21Test.java
@@ -138,7 +138,7 @@ public class Chapter21Test {
         String fib = "[1, 1, 2, 3, 5, 8, 13, 21, 34, 55]";
         TestC.run("fib", fib);
 
-        EvalRisc5 R5 = TestRisc5.build("fib", 8);
+        EvalRisc5 R5 = TestRisc5.build("fib", 9);
         int trap = R5.step(100);
         assertEquals(0,trap);
         // Return register A0 holds fib(8)==55
@@ -148,6 +148,14 @@ public class Chapter21Test {
     @Test public void testBrainFuck() throws IOException {
         String brain_fuck = "Hello World!\n";
         TestC.run("brain_fuck", brain_fuck);
+
+        EvalRisc5 R5 = TestRisc5.build("brain_fuck", 0);
+        int trap = R5.step(100000);
+        assertEquals(0,trap);
+        int ptr = (int)R5.regs[riscv.A0];
+        assertEquals(brain_fuck.length(),R5.ld4s(ptr));
+        for( int i=0; i<brain_fuck.length(); i++ )
+            assertEquals(brain_fuck.charAt(i), R5.ld1z(ptr+4+i));
     }
 
     @Test public void testPerson() throws IOException {
diff --git a/chapter21/src/test/java/com/seaofnodes/simple/EvalRisc5.java b/chapter21/src/test/java/com/seaofnodes/simple/EvalRisc5.java
index e48dd34c..7af8eaba 100644
--- a/chapter21/src/test/java/com/seaofnodes/simple/EvalRisc5.java
+++ b/chapter21/src/test/java/com/seaofnodes/simple/EvalRisc5.java
@@ -131,16 +131,15 @@ import java.util.Arrays;
                 long rs2 = regs[(ir >> 20) & 0x1f];
                 immm4 = pc + immm4 - 4;
                 rdid = 0;
-                switch( ( ir >> 12 ) & 0x7 ) {
-                    // BEQ, BNE, BLT, BGE, BLTU, BGEU
-                case 0: if( rs1 == rs2 ) pc = immm4; break;
-                case 1: if( rs1 != rs2 ) pc = immm4; break;
-                case 4: if( rs1 <  rs2 ) pc = immm4; break;
-                case 5: if( rs1 >= rs2 ) pc = immm4; break;
-                case 6: if( Long.compareUnsigned(rs1,rs2) <  0 ) pc = immm4; break;  //BLTU
-                case 7: if( Long.compareUnsigned(rs1,rs2) >= 0 ) pc = immm4; break;  //BGEU
-                default: trap = (2+1);
-                }
+                if( switch( (ir >> 12) & 0x7 ) {
+                    case 0 -> rs1 == rs2;
+                    case 1 -> rs1 != rs2;
+                    case 4 -> rs1 <  rs2;
+                    case 5 -> rs1 >= rs2;
+                    case 6 -> Long.compareUnsigned(rs1,rs2) <  0;  //BLTU
+                    case 7 -> Long.compareUnsigned(rs1,rs2) >= 0;  //BGEU
+                    default -> { trap = (2+1); yield false; }
+                    } )   pc = immm4;
                 break;
             }
             case 0x03: { // Load (0b0000011)