Fix some RISC encodings around FP spills

5 files changed, 21 insertions, 19 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java
index 61efc658..ae4a3dbe 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java
@@ -21,7 +21,9 @@ public class FltRISC extends ConstantNode implements MachNode, RIPRelSize {
         // AUIPC dst,#hi20_constant_pool
         enc.add4(riscv.u_type(riscv.OP_AUIPC, dst, 0));
         // Load dst,[dst+#low12_constant_pool]
-        enc.add4(riscv.i_type(riscv.LOAD_GPR, dst, 0b11, dst, 0));
+        enc.add4(riscv.i_type(riscv.OP_LOAD, dst, 0b11, dst, 0));
+        // Need a GPR for AUIPC, but dst is a FPR
+        throw Utils.TODO();
     }
 
     // Delta is from opcode start.
@@ -34,7 +36,7 @@ public class FltRISC extends ConstantNode implements MachNode, RIPRelSize {
         // AUIPC dst,#hi20_constant_pool
         enc.patch4(opStart  , riscv.u_type(riscv.OP_AUIPC, dst, delta));
         // Load dst,[dst+#low12_constant_pool]
-        enc.patch4(opStart+4, riscv.i_type(riscv.LOAD_GPR, dst, 0b11, dst, delta));
+        enc.patch4(opStart+4, riscv.i_type(riscv.OP_LOAD, dst, 0b11, dst, delta));
     }
 
     @Override public void asm(CodeGen code, SB sb) {
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java
index 2e0cb5d0..5519fe5b 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java
@@ -14,7 +14,7 @@ public class I2F8RISC extends MachConcreteNode implements MachNode {
     @Override public void encoding( Encoding enc ) {
         short dst  = (short)(enc.reg(this )-riscv.F_OFFSET);
         short src1 =         enc.reg(in(1));
-        int body = riscv.r_type(riscv.FLOAT_COMMON,dst,riscv.RM.RNE.ordinal(),src1,0,0x69);
+        int body = riscv.r_type(riscv.OP_FP,dst,riscv.RM.RNE.ordinal(),src1,0,0x69);
         enc.add4(body);
     }
     @Override public void asm(CodeGen code, SB sb) {
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java
index 875dd1ab..64440536 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java
@@ -23,7 +23,7 @@ public class SetFRISC extends MachConcreteNode implements MachNode {
         short dst  =         enc.reg(this );
         short src1 = (short)(enc.reg(in(1))-riscv.F_OFFSET);
         short src2 = (short)(enc.reg(in(2))-riscv.F_OFFSET);
-        int body = riscv.r_type(riscv.FLOAT_COMMON,dst,riscv.fsetop(_bop),src1,src2,0);
+        int body = riscv.r_type(riscv.OP_FP,dst,riscv.fsetop(_bop),src1,src2,0);
         enc.add4(body);
     }
 
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java
index 4188c240..ebf2d5b9 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java
@@ -22,16 +22,18 @@ public class SplitRISC extends SplitNode {
             if( src >= riscv.MAX_REG ) {
                 throw Utils.TODO(); // Very rare stack-stack move
             }
-
             int off = enc._fun.computeStackSlot(dst - riscv.MAX_REG)*8;
-            // store 64 bit values
-            enc.add4(riscv.s_type(riscv.STORE_GPR, 0b11, riscv.SP, src, off));
+            int op = srcX ? riscv.OP_STOREFP : riscv.OP_STORE;
+            if( srcX ) src -= riscv.F_OFFSET;
+            enc.add4(riscv.s_type(op, 0b011, riscv.SP, src, off));
             return;
         }
         if( src >= riscv.MAX_REG ) {
             // Load from SP
             int off = enc._fun.computeStackSlot(src - riscv.MAX_REG)*8;
-            enc.add4(riscv.i_type(riscv.LOAD_GPR, dst, 0b11,riscv.SP, off));
+            int op = dstX ? riscv.OP_LOADFP : riscv.OP_LOAD;
+            if( dstX ) dst -= riscv.F_OFFSET;
+            enc.add4(riscv.i_type(op, dst, 0b011, riscv.SP, off));
             return;
         }
         // pick opcode based on regs
@@ -40,17 +42,17 @@ public class SplitRISC extends SplitNode {
             enc.add4(riscv.r_type(riscv.OP,dst,0,src,riscv.ZERO,0));
         } else if( dstX && srcX ) {
             // FPR->FPR
-            // Can do: FPR->GPR->FPR
-            enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst, 0, src - riscv.F_OFFSET, 0, 0b1110001));
-            enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst - riscv.F_OFFSET, 0, src, 0, 0b0100000));
+            src -= riscv.F_OFFSET;
+            dst -= riscv.F_OFFSET;
+            enc.add4(riscv.r_type(riscv.OP_FP, dst, 0b000, src, src, 0b0010101)); // dst = FMIN(src,src)
         } else if(!srcX && dstX) {
             //GPR->FPR
             // fmv.d.x
-            enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst - riscv.F_OFFSET, 0, src, 0, 0b1111001));
+            enc.add4(riscv.r_type(riscv.OP_FP, dst - riscv.F_OFFSET, 0, src, 0, 0b1111001));
         } else if(srcX && !dstX) {
             //FPR->GPR
             //fmv.x.d
-            enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst, 0, src - riscv.F_OFFSET, 0, 0b1110001));
+            enc.add4(riscv.r_type(riscv.OP_FP, dst, 0, src - riscv.F_OFFSET, 0, 0b1110001));
         }
 
     }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index 56da1811..93b18a01 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -103,9 +103,13 @@ public class riscv extends Machine {
     };
 
     // major opcode: OP
+    public static int OP_LOAD    = 0b00_000_11;
+    public static int OP_LOADFP  = 0b00_001_11;
     public static int OP_CUSTOM0 = 0b00_010_11;
     public static int OP_AUIPC   = 0b00_101_11;
 
+    public static int OP_STORE   = 0b01_000_11;
+    public static int OP_STOREFP = 0b01_001_11;
     public static int OP_CUSTOM1 = 0b01_010_11;
     public static int OP         = 0b01_100_11;
     public static int OP_LUI     = 0b01_101_11;
@@ -118,13 +122,7 @@ public class riscv extends Machine {
 
     public static int OP_CALL    = 0b11_001_11;
 
-    // major opcode: Store-Load
-    public static int LOAD_FLOAT  = 0b00_001_11;
-    public static int LOAD_GPR    = 0b00_000_11;
-    public static int STORE_FLOAT = 0b01_001_11;
-    public static int STORE_GPR   = 0b01_000_11;
 
-    public static int FLOAT_COMMON = 0b10_100_11;
 
     //I_type opcode: 0010 0011
     public static int I_TYPE = 0x13;