Get SLT[IU]* working (#192)

3 files changed, 12 insertions, 9 deletions

diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java
index 3f224d05..8cec13f9 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java
@@ -6,12 +6,12 @@ import com.seaofnodes.simple.node.Node;
 // corresponds to slti,sltiu
 public class SetIRISC extends ImmRISC {
     final boolean _unsigned;    // slti vs sltiu
-    SetIRISC( Node src, int imm12, boolean unsigned ) {
+    public SetIRISC( Node src, int imm12, boolean unsigned ) {
         super(src,imm12);
         _unsigned = unsigned;
     }
-    @Override public String op() { return "setlt" + (_unsigned ? "u":""); }
+    @Override public String op() { return "slt" + (_unsigned ? "u":"") + "i"; }
     @Override public String glabel() { return  "<"+ (_unsigned ? "u":""); }
-    @Override int opcode() { return 19; }
-    @Override int func3() { return 2; }
+    @Override int opcode() { return 0b0010011; }
+    @Override int func3() { return _unsigned ? 0b011 : 0x010; }
 }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java
index e81e363e..2cd1bac0 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java
@@ -6,11 +6,14 @@ import com.seaofnodes.simple.node.*;
 
 // corresponds to slt (and NOT sltu, slti, sltiu)
 public class SetRISC extends MachConcreteNode implements MachNode {
-    SetRISC( Node cmp ) { super(cmp); }
-    @Override public String op() { return "slt"; }
+    final boolean _unsigned;
+    public SetRISC( Node cmp, boolean unsigned ) { super(cmp); _unsigned=unsigned; }
+    @Override public String op() { return "slt" + (_unsigned ? "u":""); }
     @Override public RegMask regmap(int i) { return riscv.RMASK; }
     @Override public RegMask outregmap() { return riscv.WMASK; }
-    @Override public void encoding( Encoding enc ) { riscv.r_type(enc,this,2,0); }
+    @Override public void encoding( Encoding enc ) {
+        riscv.r_type(enc,this,_unsigned ? 0b011 : 0x010,0);
+    }
     @Override public void asm(CodeGen code, SB sb) {
         sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" < ").p(code.reg(in(2)));
     }
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index dea2d530..9006c614 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -451,9 +451,9 @@ public class riscv extends Machine {
         return switch( bool.op() ) {
         case "<" -> bool.in(2) instanceof ConstantNode con && con._con instanceof TypeInteger ti && imm12(ti)
             ? new SetIRISC(bool, (int)ti.value(),false)
-            : new SetRISC(bool);
+            : new SetRISC(bool, false);
         // x <= y - flip and invert; !(y < x); `slt tmp=y,x; xori dst=tmp,#1`
-        case "<=" -> new XorIRISC(new SetRISC(bool.swap12()),1);
+        case "<=" -> new XorIRISC(new SetRISC(bool.swap12(), false),1);
         // x == y - sub and vs0 == `sub tmp=x-y; sltu dst=tmp,#1`
         case "==" -> new SetIRISC(new SubRISC(bool),1,true);
         default -> throw Utils.TODO();