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authorCliff Click <cliffc@acm.org>2025-03-15 12:55:57 -0700
committerCliff Click <cliffc@acm.org>2025-03-15 12:55:57 -0700
commitfe27a3326becaf1a59286fa03d9aaa22504ec4ee (patch)
tree1b4d24125db9a4554335ff911e8c100c89f11965 /chapter21/src
parentb6cbd3d7b7698922e60e2c3eadadab51a430efe1 (diff)
downloadSimple-fe27a3326becaf1a59286fa03d9aaa22504ec4ee.tar.gz
Simple-fe27a3326becaf1a59286fa03d9aaa22504ec4ee.zip
Tests all pass
Diffstat (limited to 'chapter21/src')
-rw-r--r--chapter21/src/main/java/com/seaofnodes/simple/codegen/IFG.java9
-rw-r--r--chapter21/src/test/java/com/seaofnodes/simple/BrainFuckTest.java2
2 files changed, 9 insertions, 2 deletions
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/codegen/IFG.java b/chapter21/src/main/java/com/seaofnodes/simple/codegen/IFG.java
index bd6c2d56..729ec88e 100644
--- a/chapter21/src/main/java/com/seaofnodes/simple/codegen/IFG.java
+++ b/chapter21/src/main/java/com/seaofnodes/simple/codegen/IFG.java
@@ -207,8 +207,15 @@ abstract public class IFG {
// Disallow clone-ables from killing registers. Just fail
// them and re-clone closer to target... so no kill.
// Special case for Intel XOR used to zero.
- if( m.isClone() )
+ Node n = (Node)m;
+ CFGNode effUseBlk = n.out(0) instanceof PhiNode phi ? phi.region().cfg(phi._inputs.find(n)) : n.out(0).cfg0();
+ if( m.isClone() && // Must be clonable
+ (n.nOuts()>1 || // Has many users OR
+ // Only 1 user but effective use is remote block
+ effUseBlk != n.cfg0() ))
+ // Then fail the clonable; it should split or move
alloc.fail(alloc.lrg((Node)m));
+ // Else clonable cannot move
else if( !tlrg.sub(killMask) )
alloc.fail(tlrg);
}
diff --git a/chapter21/src/test/java/com/seaofnodes/simple/BrainFuckTest.java b/chapter21/src/test/java/com/seaofnodes/simple/BrainFuckTest.java
index c23bb301..dd1f2372 100644
--- a/chapter21/src/test/java/com/seaofnodes/simple/BrainFuckTest.java
+++ b/chapter21/src/test/java/com/seaofnodes/simple/BrainFuckTest.java
@@ -64,7 +64,7 @@ for( int pc = 0; pc < program#; pc++ ) {
return output;
""";
Chapter20Test.testCPU(src,"x86_64_v2", "SystemV",28,null);
- Chapter20Test.testCPU(src,"riscv" , "SystemV",18,null);
+ Chapter20Test.testCPU(src,"riscv" , "SystemV",14,null);
Chapter20Test.testCPU(src,"arm" , "SystemV",12,null);
//assertEquals("Hello World!\n", Eval2.eval(code, 0, 10000));
}