cleanup SRA & WS

6 files changed, 12 insertions, 24 deletions

diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/StoreNode.java b/chapter22/src/main/java/com/seaofnodes/simple/node/StoreNode.java
index 6e92c67a..87190f37 100644
--- a/chapter22/src/main/java/com/seaofnodes/simple/node/StoreNode.java
+++ b/chapter22/src/main/java/com/seaofnodes/simple/node/StoreNode.java
@@ -85,15 +85,16 @@ public class StoreNode extends MemOpNode {
         }
 
         if( val() instanceof SarNode shr &&
-                shr.in(1) instanceof ShlNode shl &&
-                shr.in(2)._type.isConstant() &&
-                shl.in(2)._type.isConstant() ) {
+            shr.in(1) instanceof ShlNode shl &&
+            shr.in(2)._type.isConstant() &&
+            shl.in(2)._type.isConstant() ) {
 
             ConstantNode shr_s = (ConstantNode)(shr.in(2));
             ConstantNode shl_s = (ConstantNode)(shl.in(2));
 
             if( shl_s._type == shr_s._type )
-                return setDef(3, shl.in(1));
+                //return setDef(3, shl.in(1));
+                throw Utils.TODO();
         }
 
         return null;
diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/ImmRISC.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/ImmRISC.java
index d77a4ff9..589bf550 100644
--- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/ImmRISC.java
+++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/ImmRISC.java
@@ -40,14 +40,7 @@ abstract public class ImmRISC extends MachConcreteNode implements MachNode {
     @Override public void encoding( Encoding enc ) {
         short dst = enc.reg(this );
         short src = enc.reg(in(1));
-        // special case for SRAI
-        if(this instanceof SraIRISC) {
-            int body = riscv.sra_i_type(opcode(), dst, func3(), src, _imm12 & 0xFFF);
-            enc.add4(body);
-            return;
-        }
-        int body = riscv.i_type(opcode(), dst, func3(), src, _imm12 & 0xFFF);
-        enc.add4(body);
+        enc.add4(riscv.i_type(opcode(), dst, func3(), src, _imm12));
     }
 
     // General form: "addi  rd = rs1 + imm"
diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java
index 26404e95..1533003c 100644
--- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java
+++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java
@@ -4,7 +4,9 @@ import com.seaofnodes.simple.Utils;
 import com.seaofnodes.simple.node.Node;
 
 public class SraIRISC extends ImmRISC {
-    public SraIRISC( Node and, int imm) { super(and,imm); }
+    public SraIRISC( Node and, int imm) {
+        super(and,imm | (0x20 << 5));
+    }
     @Override int opcode() {  return riscv.OP_IMM; }
     @Override int func3() {  return 5;}
     @Override public String glabel() { return ">>"; }
diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java
index cef56f6a..d34d94fc 100644
--- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java
+++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java
@@ -19,7 +19,7 @@ import com.seaofnodes.simple.node.*;
 
 // sw rs2,offset(rs1)
 public class StoreRISC extends MemOpRISC {
-    StoreRISC( StoreNode st, Node base, int off, Node val ) { super(st, base, off, val);}
+    StoreRISC( StoreNode st, Node base, int off, Node val ) { super(st, base, off, val); }
     @Override public String op() { return "st"+_sz; }
     @Override public RegMask regmap(int i) {
         // 0 - ctrl
diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index 9db6bd5a..743e2e1f 100644
--- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -188,13 +188,6 @@ public class riscv extends Machine {
         return  (imm12 << 20) | (rs1 << 15) | (func3 << 12) | (rd << 7) | opcode;
     }
 
-    public static int sra_i_type(int opcode, int rd, int func3, int rs1, int imm12) {
-        assert 0 <= rd  &&  rd  < 32;
-        assert 0 <= rs1 &&  rs1 < 32;
-        assert opcode >= 0 && func3 >=0 && imm12 >= 0; // Zero-extend by caller
-        return  (((0x20 << 5) | imm12) << 20) | (rs1 << 15) | (func3 << 12) | (rd << 7) | opcode;
-    }
-
     // S-type instructions(store)
     public static int s_type(int opcode, int func3, int rs1, int rs2, int imm12) {
         assert 0 <= rs1 &&  rs1 < 32;
diff --git a/chapter22/src/test/java/com/seaofnodes/simple/Chapter20Test.java b/chapter22/src/test/java/com/seaofnodes/simple/Chapter20Test.java
index baee39fe..e14c323f 100644
--- a/chapter22/src/test/java/com/seaofnodes/simple/Chapter20Test.java
+++ b/chapter22/src/test/java/com/seaofnodes/simple/Chapter20Test.java
@@ -63,9 +63,8 @@ val sqrt = { int x ->
         guess = next;
     }
 };
-int truncate_me = (arg+2);
-int truncate = arg;
-return sqrt(truncate) + sqrt(truncate_me);
+int cast_int = arg+2;
+return sqrt(arg) + sqrt(cast_int);
 """;
         testCPU(src,"x86_64_v2", "Win64"  ,23,null);
         testCPU(src,"riscv"    , "SystemV",19,null);