ch23 changes (#222)

* fixed main pr problems

* regmask extra comments

* Clean pass normal tests

New fcn print upgrades several golden rule tests.
Move the unlink-all from the walk::err call (which IS used during IterPeeps) to GCM.
CallEnd upgrades return type based on constant call.
Fix unlink to also unlink CallEnd
Constant TFP print checks constant
Tested an untested Load

* Arm basics, minor changes in riscv (#160)

* Initial push

Major CodeGen cleanup; most static globals move into the CodeGen object.

* Minor progress bug with mutual recursion

* Add test from pr#148

* First cut x86 "port"

Only "return 0;", no registers, no encoding, but yah gotta start somewhere

* Update README.md

* Update README.md

* Update ListScheduler.java

* command line launcher for simple

Parser bug fref in args
Some new test cases.

* Add basic RegMask for more than 64 bits of register mask.

Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension

* ASM Printer

InstSel handles folding 2+ ideal ops into 1 machine op

* handle instSel for some control flow

Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.

* Basic if-block inst selects and asm prints

* Add mul-by-coinstant to shift

* left shift codegen basic

* exclude RSP from *write* mask

* 2-arg add (not immediate)

mul-by-small constant opt.  Some utilities.

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* inst select for new struct allocation

* Float, bitwise and arithmetic operands codegen x86-64 (#150)

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* Handle first loop

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates

* float ops without imm values

* merge

* merge

* inst select for new struct allocation

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* Remove non-exsting FP+imm ops

* left shift codegen basic

* sar codegen basic

* merge

* some basic ops

* addf

* divf, subf, mulf

* rsp allowed in bitwise input, not output

* formatting

* float ops without imm values

* merge

* merge

* Rebased on ch 19

* Update tests

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* cleanup after merge

alpha-sort helper fcns
implicit test vs zero/null

* Add LEA op

asm print works on ideal nodes for all tests

* Minor cleanup lea

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* x86 addressing modes during inst select

Drop New taking inits; just follow with initializing stores.  Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate

* call setup

* extended ch13, 14,15,16 (#153)

* merge2

* merge3

* Fix a few minor fuzzer bugs

* Force array layout

ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.

* Fix a bunch of float issues

was deleting required inputs

* simpler invariant

defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).

* Call & CallR X86 instructions

* merge2

* Add-from-memory op

Remove FP immediate forms.

* Remove name from TFP

Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

* New (#154)

* merge2

* merge3

* GCM for float ops fixed, other cleanup - small extensions

* call setup

* merge2

* remove debug prints

add check for bad call convention
fix 3 tests (bad merge?)

* cleanup call convention abi

Needs more love at some point...

* one more cleanup ABI

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Add CmpMem form

Common addressing mode print
LEA can skip a base

* Add a AddFMemX86

A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.

* Docs

* XMM reg mask fix

Minor README updates

* Allow inverted cmp/mem

narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info

* Support "*ptr op= val"

at least for MemAdd

* missed golden rule update

* Array len is u32

load-after-store zero/sign-extends if the store is truncating

* One more missed case

* riscv init

* added not imm form bitwise shifts and ops plus test cases

* addressing modes(high chance it'll get deleted)

* fix minor bug

* delete non existing matches

* replace RegMask.Empty with null

* riscv handle store and load, fltRisch uses risc reg now

* load float into GPR and then later in RA do hard split.

* minor changes

* turn off ch20 tests

* Update Chapter20Test.java

* add riscv port to readme

* arm init

* work in progress

* arm2 bs

* work in progress

* clearnup arm

* fixed main pr problems

* regmask extra comments

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

* Update Chapter20Test.java

* Weaken range-check test

since no range checks... test cannot fail (pass)

* Fix issue #161

Error adding 'null' and '5'

* bug fixs, cloning constants

Fix bug missing Find.
Fix bug setDef does unordered removal from basic blocks.
Use cloned constants for spilling.

* RA fixes

SplitSelfConflict MUST split before uses and after defs.
Split global constants across functions
Missing find in union;
Inserting split after new inserted wrong place
Pre-remove null LRGs before color.
Bias color hunts through Phis
Shorten InstructionSelection.
Rename !unified() to leader()
AddMemX86 is 2-addr
Add CastXXX to preserve register across cast.

* encoding init

* encoding init 2

* rex fix

* indirect addressing modes

* setop change opcode, rename FLOAT_OFFSET

* mask sib and modrm with 3 bits, 4th bit goes into rex.

* sign extend div with cqo

* idiv input is fixed to rax and RMASK, grab input from second slot when encoding

* encoding of newx86

* tfp and CallEndNode encoding

* sib improvement

* more cleanups

* more cleanups

* Allow a killMap to kill regs.

Bugfix scheduler.
Bugfix spiller - self-conflict order depended on hashtable iteration order, which depended on System.hashCode which would vary run to run.
Improvements to coloring
Improvements to spill quality testing

* Added flags-kill for XOR

* Missing add-deps from fuzzer

* Update Chapter14Test.java

* fixed order of operands

* base rex fixup

* more bug fix

* remove jukn files

* minimal "make release"

* further fixes

* minor fixes

* minor fixes

* minor fixes

* base != -1 check, precedence fix

* Add regkills in IFG building

Fix bug LRG union stats
Adjust self-conflict splits to be slightly less aggressive
In every use-side split, dont split-after-split same block.
NewNode is a multi, does not define a register

* 64 bit encoding for gpr(s) load

* RA improvements

Attempt to commute to keep reg-masks compatible.
Clones with kills (x86 XOR killing flags to zero) fail before the flag-def.
Bugfix failed to color last lrg.
More smarts on picking trivial LRGs during coloring
Drop isSplit, add SplitNode
Pass regalloc round to all splits for debugging
Self-conflict no split on loop backedge.
Handle split that gets made goes dead
No-reg-mask spilling handles case with many def/uses.
Add DivIX86
BrainFuck, MergeSort now allocate as testing

* 8 bit imm support

* conditional jump fix

* Push l,ast change, unbreak branch

* XOR remove extra opcode, imm size supports 8 bit.

* Finally pass the `new [u8]` double-copy test

* Fix several ARM reg setup problems

Finish Split bypass check
ARM: rsp is also a fixed zero, in R31.  R0 is a valid register.
CallArm prints args, passes TFP for arg selection.  Does not return a register.  All CallEndARM which DOES return a register.  Parms missing tfp for float args.  ProjARM after a New missing regs.  RetARM missing RPC.
Remove hopeful DivIX86

* 64 bit imm for alu ops encoded in extra reg then use it in Op as an operand

* Bunch of minor arm, risc fixes

small constants not cloning

* jump invert encoding

* warning comment

* Much ARM fixage

One More Go-Round with Better Biased Colors
Fix bug picking deepest spills to bias.
ARM: remove default 2-address.  Fix regmask overflow.  Rename some ops to be canonical.

* Fixes to release

Port does not have to be in a Simple named directory.
Call convention is just a string, no enum
Missed some tests running RISC, ARM.

* Minor release change to allow another foreign port

* better split encoding and fix CallInMask

* notNode

* fix callInMask

* riscv init

* riscv basic ALU ops and types of instructions

* Allowing non-Simple repo ports

Expanding public API slightly so alternative (non-Simple repo) ports can happen.
RegMask supports single-bit-set and a long bitmask.
Bugfix GCM splitting multiple global constants.
Bugfix LCM grabbing a projection vs multi
Bugfix RegAlloc when avoiding splitting a clonable
Source code in release
More timing in CodeGen

* riscv indirect addressing and function calls

* Cleanup call ABI presentation

Everybody uses the same names, same code shapes

* Caller save regs

...not callee save yet

* Expose caller save regs

* Store Risc adjustments, no imm in MemOpRISC

* specific print encoding for cpus

* merge fixup

* More x86,risc,arm call convention fixes

Collect callee and caller save masks (inverts of each other, except for spills).
Reorg layout to be closer to each other; remove dead mask definitions; add final keyword

* lui fix up with 32 bit immediates

* Callee-save registers

Callee-save registers and masks and inserting LRGs for same and spilling and picking good spills.  Insert CalleeSaveNodes and edges to RetXXXs and RegMasks for those edges.
Iterators for regmask.
Better printing post-allocation

* RegMask supports 128 bits

All regs available arm, risc.
MergeSort compiles & runs

* added flags splitting

* Fix risc5 compares

No flags on risc5.
Branch takes 2 inputs (one can be imm12).
Float compare only sets a GPR to 0/1.
Bool has a isFloat
Common risc5 imm-form handling

* extend test cases

* imm encoding, flags fixed

* grep for Todo: relocs

* float riscv fixed

* flags for set

* lui fix for small bits [0, 12]

* arm init

* arm last touches

* fmov still needs fix

* minor fixes

* minor fixes(2)

* got rid of unnecessary stuff

* create ch21

* remove encodings from chapter20 dir

* 1/2 pass cleaning up ARM encoding API

* ARM encoding compiles

* Risc R_TYPE and I_TYPE

* Progress RISC encodings

Missing lots of stuff still

* progress risc encoding

* risc encodings compile

* Update README.md

* Fold up redundant OP/OP-FP risc5 encoding

* x86 mem opcodes first cut

break out MemOp encodings into parts; change x86 indirectAdr to use Encoding class, remove redundant asserts & code

* x86 mem op encodings

* x86 reg+imm forms

* most reg-reg forms

* More x86 encodings

* Last few encodings

* switch to binary literals over decimals for opcodes

* logical immediates fixed, bitwise ops imm forms

* tfp and setArm fixed

* PC relative float for riscv

* readme init

* Merged pr/169

* Fixed the array1 test encodings

Clean up branch invert logic during BB layout
Cleanup branch target printing for RISC,ARM
ImmRISC ops mask imm12 to 12 bits
Fix NewRISC; hardcode RPC as part of call
Fix RISC inverting branchs >,>=

* floatarm encoding

* tfparm and intarm

* uncontional jump encoding for arm and riscv

* smarter IntARM, Intx86 does not always include rex.

* REX after PREFIX

* fixup load and store indirect

* updated rex prefix, if its 0x40 then its not needed

* Rex fix for floats, got rid of unnecessary stuff.

* rename to camel case, better param name

* add test export

* merged

* store opt

* store and load optimised forms handled

* tfp patch

* Store/load float arm/riscv/x64

* got rid of debug print

* splits for x86, riscv and arm

* readme fixups

* fix global symbol numbering for constants

* fix TFP pathc on arm and riscv, keep symbols in good order.

* fix opcode for store and loads, memOpRisc for Store and splitting

* replace hard coded opcodes with major opcodes

* replace hard coded opcodes with major opcodes

* add asserts and fix reg numbering

* add asserts and fix reg numbering

* minor updates

* revert changes

* remove constant pool from encoder TODO: add flag for JIT

* extend test cases

* minor fixes

* minor fixes

* update float test case

* stringHash fix on x64

* remove conditional ConstantPool write

* brainfuck minor fixes

* minor arm fixes

* split fix

* brainfuck and fib

* brain fuck

* arg_count, person

* add ignore

* typo

* riscv test sieve attempt

* minor changes

* riscv5 emulator additions

* arm eval setup

* Update riscv.java

* arm eval basics

* delta fixes

* arm fixes

* testfib arm

* arg_count

* small update for test newton

* small update for test newton

* testNewton runs on x64, riscv and arm

* arm additions

* arm pc eval fix

* arm workings

* debugging

* Progress sieve on ARM

Most ops need WMASK as the output, to exclude RSP.
calloc sentinal changes to multiple of 4
NewArm needs to set arg X0 to #1; arg X1 is length.
Fix EvalARM calling calloc & not advancing PC.
Fix EvalARM using ints vs longs.
Fix EvalARM missing AndI encoding.

* Fix some arm encoding

Fix some OBOB in R5 calloc encoding.
Sort EvalArm by major opcodes.
Add ASL.  Remove leading switch.  Fix OBOB in calloc.
Fix shift in ld/st with reg+offset

* arm sieve test

* test person push

* brainFuck arm

* "and" "or" syntactic sugar

* update encoding

* ch23 `and` `or`

* hack parse trinary for and, or

* close

* fixed or issue

* Update CallEndNode.java

* fix type issue

* fixed

* Adjust parseTrinary precedence vs && ||

* Fix arm simulation return

* Formatting

* Formatting

* simplify rn to be always 0.

---------

Co-authored-by: Cliff Click <cliffc@acm.org>

8 files changed, 63 insertions, 21 deletions

diff --git a/chapter23/src/main/java/com/seaofnodes/simple/Parser.java b/chapter23/src/main/java/com/seaofnodes/simple/Parser.java
index 1db873e0..ffd4bfe9 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/Parser.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/Parser.java
@@ -530,11 +530,11 @@ public class Parser {
         // Parse predicate
         require("(");
         var pred = require(parseAsgn(), ")");
-        return parseTrinary(pred,true,"else");
+        return parseTrinary(pred,"else");
     }
 
     // Parse a conditional expression, merging results.
-    private Node parseTrinary( Node pred, boolean stmt, String fside ) {
+    private Node parseTrinary( Node pred, String fside ) {
         pred.keep();
 
         // IfNode takes current control and predicate
@@ -550,7 +550,15 @@ public class Parser {
         // Parse the true side
         ctrl(ifT.unkeep());     // set ctrl token to ifTrue projection
         _scope.addGuards(ifT,pred,false); // Up-cast predicate
-        Node lhs = (stmt ? parseStatement() : parseAsgn()).keep(); // Parse true-side
+        // Parse true-side flavor
+        Node lhs = switch( fside ) {
+        case "else" -> parseStatement(); // if( pred )  stmts;
+        case ":"    -> parseAsgn();      //     pred ?  asgn;
+        case "&&"   -> parseLogical();   //     pred && expr
+        case "||"   -> pred;             //     pred || expr_is_ignored
+        default     -> throw Utils.TODO();
+        };
+        lhs.keep();
         _scope.removeGuards(ifT);
 
         // See if a one-sided def was made: "if(pred) int x = 1;" and throw.
@@ -566,17 +574,23 @@ public class Parser {
         // Up-cast predicate, even if not else clause, because predicate can
         // remain true if the true clause exits: `if( !ptr ) return 0; return ptr.fld;`
         _scope.addGuards(ifF,pred,true);
-        boolean doRHS = match(fside);
-        Node rhs = (doRHS
-            ? (stmt ? parseStatement() : parseAsgn())
-            : con(lhs._type.makeZero())).keep();
+        // Parse false-side flavor
+        boolean doRHS = false;  // RHS is optional for if/else and trinary
+        Node rhs = switch( fside ) {
+        case "else" -> (doRHS=match(fside)) ? parseStatement() : con(lhs._type.makeZero());
+        case ":"    -> (doRHS=match(fside)) ? parseAsgn()      : con(lhs._type.makeZero());
+        case "&&"   -> rhs = pred;
+        case "||"   -> rhs = parseLogical();
+        default     -> throw Utils.TODO();
+        };
+        rhs.keep();
         _scope.removeGuards(ifF);
         if( doRHS )
             fScope = _scope;
         pred.unkeep();
 
         // Check the trinary widening int/flt
-        if( !stmt ) {
+        if( !fside.equals("else") ) {
             rhs = widenInt( rhs.unkeep(), lhs._type ).keep();
             lhs = widenInt( lhs.unkeep(), rhs._type ).keep();
         }
@@ -593,7 +607,7 @@ public class Parser {
         Node ret = peep(new PhiNode("",lhs._type.meet(rhs._type).glb(false),r,lhs.unkeep(),rhs.unkeep()));
         // Immediately fail e.g. `arg ? 7 : ptr`
         ParseException err;
-        if( !stmt && (err=ret.err()) !=null )  throw err;
+        if( !fside.equals("else") && (err=ret.err()) !=null )  throw err;
         r.peephole();
         return ret;
     }
@@ -993,8 +1007,8 @@ public class Parser {
      * @return an expression {@link Node}, never {@code null}
      */
     private Node parseExpression() {
-        Node expr = parseBitwise();
-        return match("?") ? parseTrinary(expr,false,":") : expr;
+        Node expr = parseLogical();
+        return match("?") ? parseTrinary(expr,":") : expr;
     }
 
     /**
@@ -1005,13 +1019,25 @@ public class Parser {
      * </pre>
      * @return a bitwise expression {@link Node}, never {@code null}
      */
+
+    private Node parseLogical() {
+        Node lhs = parseBitwise();
+        while (true) {
+            if( false ) ;
+            else if( match("&&") ) lhs = parseTrinary(lhs, "&&");
+            else if( match("||") ) lhs = parseTrinary(lhs, "||");
+            else break;
+        }
+        return lhs;
+    }
+
     private Node parseBitwise() {
         Node lhs = parseComparison();
         while( true ) {
             if( false ) ;
-            else if( match("&") ) lhs = new AndNode(loc(),lhs,null);
-            else if( match("|") ) lhs = new  OrNode(loc(),lhs,null);
-            else if( match("^") ) lhs = new XorNode(loc(),lhs,null);
+            else if( matchOp('&') ) lhs = new AndNode(loc(),lhs,null);
+            else if( matchOp('|') ) lhs = new  OrNode(loc(),lhs,null);
+            else if( match  ("^") ) lhs = new XorNode(loc(),lhs,null);
             else break;
             lhs.setDef(2,parseComparison());
             lhs = peep(lhs);
@@ -1701,6 +1727,7 @@ public class Parser {
     private boolean match (String syntax) { return _lexer.match (syntax); }
     // Match must be "exact", not be followed by more id letters
     private boolean matchx(String syntax) { return _lexer.matchx(syntax); }
+    private boolean matchOp(char c0 ) { return _lexer.matchOp(c0);  }
     private boolean matchOpx(char c0, char c1) { return _lexer.matchOpx(c0,c1);  }
     // Return true and do NOT skip if 'ch' is next
     private boolean peek(char ch) { return _lexer.peek(ch); }
@@ -1876,6 +1903,15 @@ public class Parser {
             _position -= syntax.length();
             return false;
         }
+        // Match this char, and the next char must be different.
+        // Handles '&&' vs '&'
+        boolean matchOp( char c0 ) {
+            skipWhiteSpace();
+            if( _position+1 >= _input.length || _input[_position]!=c0 || _input[_position+1]==c0 )
+                return false;
+            inc();
+            return true;
+        }
         // Match these two characters in a row
         boolean matchOpx(char c0, char c1) {
             skipWhiteSpace();
diff --git a/chapter23/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java b/chapter23/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java
index caa7ff44..6c958f32 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java
@@ -39,6 +39,8 @@ public class CodeGen {
 
     // ---------------------------
     public CodeGen( String src ) { this(src, TypeInteger.BOT, 123L, true ); }
+    public CodeGen( String src, TypeInteger arg) { this(src, arg==null ? TypeInteger.BOT : arg, 123L, true ); }
+
     public CodeGen( String src, TypeInteger arg, long workListSeed, boolean reset ) {
         CODE = this;
         if( reset ) Type.reset();
diff --git a/chapter23/src/main/java/com/seaofnodes/simple/node/CallEndNode.java b/chapter23/src/main/java/com/seaofnodes/simple/node/CallEndNode.java
index b75852a4..d95af697 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/node/CallEndNode.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/node/CallEndNode.java
@@ -86,6 +86,11 @@ public class CallEndNode extends CFGNode implements MultiNode {
                         fun.setDef(2,call.ctrl());  // Bypass the Call;
                         fun.ret().setDef(3,null);   // Return is folding also
                         CodeGen.CODE.addAll(fun._outputs);
+                        // Repeat defs 1 layer down, for users of Parm (Phis)
+                        for( Node parm : fun._outputs )
+                            if( parm instanceof ParmNode )
+                                CodeGen.CODE.addAll(parm._outputs);
+
                         // Inlining immediately blows all cache idepth fields past the inline point.
                         // Bump the global version number invalidating them en-masse.
                         CodeGen.CODE.invalidateIDepthCaches();
diff --git a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java
index a2cb9bba..427cf2e2 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java
@@ -42,9 +42,9 @@ public class CallARM extends CallNode implements MachNode, RIPRelSize {
     }
 
     @Override public void asm(CodeGen code, SB sb) {
-        sb.p(_name);
+        sb.p(_name).p("  ");
         for( int i=0; i<nargs(); i++ )
-            sb.p(code.reg(arg(i+2))).p("  ");
+            sb.p(code.reg(arg(i+2))).p(", ");
         sb.unchar(2);
     }
 }
diff --git a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java
index a3e1cf19..c84aa9e5 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java
@@ -25,7 +25,7 @@ public class CallRRARM extends CallNode implements MachNode {
     @Override public void asm(CodeGen code, SB sb) {
         sb.p(code.reg(fptr())).p("  ");
         for( int i=0; i<nargs(); i++ )
-            sb.p(code.reg(arg(i))).p("  ");
+            sb.p(code.reg(arg(i))).p(", ");
         sb.unchar(2);
     }
 
diff --git a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java
index a676ba60..bd5dabe5 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java
@@ -57,7 +57,6 @@ public class CallRISC extends CallNode implements MachNode, RIPRelSize {
         sb.p(_name).p("  ");
         for( int i=0; i<nargs(); i++ )
             sb.p(code.reg(arg(i+2))).p(", ");
-        sb.unchar(2).p("  ").p(code.reg(fptr()));
-
+        sb.unchar(2);
     }
 }
diff --git a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java
index ac36ed12..298789e8 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java
@@ -25,7 +25,7 @@ public class CallRRISC extends CallNode implements MachNode {
     @Override public void asm(CodeGen code, SB sb) {
         sb.p(code.reg(fptr())).p("  ");
         for( int i=0; i<nargs(); i++ )
-            sb.p(code.reg(arg(i))).p("  ");
+            sb.p(code.reg(arg(i))).p(", ");
         sb.unchar(2);
     }
 }
diff --git a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/CallX86.java b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/CallX86.java
index ffdce7df..d74e3833 100644
--- a/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/CallX86.java
+++ b/chapter23/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/CallX86.java
@@ -42,7 +42,7 @@ public class CallX86 extends CallNode implements MachNode, RIPRelSize {
     @Override public void asm(CodeGen code, SB sb) {
         sb.p(_name).p("  ");
         for( int i=0; i<nargs(); i++ )
-            sb.p(code.reg(in(i+2))).p("  ");
+            sb.p(code.reg(in(i+2))).p(", ");
         sb.unchar(2);
     }
 }