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| author | Cliff Click <cliffc@acm.org> | 2025-09-22 10:08:43 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-22 10:08:43 -0700 |
| commit | e5acc8a2127432d19ff43e420602f24fafa8d51b (patch) | |
| tree | 75b0ff3f8da398bfff938335051379fce12605ac /chapter23/src/main/java | |
| parent | be282a0d8948706d7110b72fe745bcb4ceb02b3a (diff) | |
| download | Simple-e5acc8a2127432d19ff43e420602f24fafa8d51b.tar.gz Simple-e5acc8a2127432d19ff43e420602f24fafa8d51b.zip | |
Chaining Conditionals and SCCP (#230)
* merge fixup
* More x86,risc,arm call convention fixes
Collect callee and caller save masks (inverts of each other, except for spills).
Reorg layout to be closer to each other; remove dead mask definitions; add final keyword
* lui fix up with 32 bit immediates
* Callee-save registers
Callee-save registers and masks and inserting LRGs for same and spilling and picking good spills. Insert CalleeSaveNodes and edges to RetXXXs and RegMasks for those edges.
Iterators for regmask.
Better printing post-allocation
* RegMask supports 128 bits
All regs available arm, risc.
MergeSort compiles & runs
* added flags splitting
* Fix risc5 compares
No flags on risc5.
Branch takes 2 inputs (one can be imm12).
Float compare only sets a GPR to 0/1.
Bool has a isFloat
Common risc5 imm-form handling
* extend test cases
* imm encoding, flags fixed
* grep for Todo: relocs
* float riscv fixed
* flags for set
* lui fix for small bits [0, 12]
* arm init
* arm last touches
* fmov still needs fix
* minor fixes
* minor fixes(2)
* got rid of unnecessary stuff
* create ch21
* remove encodings from chapter20 dir
* 1/2 pass cleaning up ARM encoding API
* ARM encoding compiles
* Risc R_TYPE and I_TYPE
* Progress RISC encodings
Missing lots of stuff still
* progress risc encoding
* risc encodings compile
* Update README.md
* Fold up redundant OP/OP-FP risc5 encoding
* x86 mem opcodes first cut
break out MemOp encodings into parts; change x86 indirectAdr to use Encoding class, remove redundant asserts & code
* x86 mem op encodings
* x86 reg+imm forms
* most reg-reg forms
* More x86 encodings
* Last few encodings
* switch to binary literals over decimals for opcodes
* logical immediates fixed, bitwise ops imm forms
* tfp and setArm fixed
* PC relative float for riscv
* readme init
* Merged pr/169
* Fixed the array1 test encodings
Clean up branch invert logic during BB layout
Cleanup branch target printing for RISC,ARM
ImmRISC ops mask imm12 to 12 bits
Fix NewRISC; hardcode RPC as part of call
Fix RISC inverting branchs >,>=
* floatarm encoding
* tfparm and intarm
* uncontional jump encoding for arm and riscv
* smarter IntARM, Intx86 does not always include rex.
* REX after PREFIX
* fixup load and store indirect
* updated rex prefix, if its 0x40 then its not needed
* Rex fix for floats, got rid of unnecessary stuff.
* rename to camel case, better param name
* add test export
* merged
* store opt
* store and load optimised forms handled
* tfp patch
* Store/load float arm/riscv/x64
* got rid of debug print
* splits for x86, riscv and arm
* readme fixups
* fix global symbol numbering for constants
* fix TFP pathc on arm and riscv, keep symbols in good order.
* fix opcode for store and loads, memOpRisc for Store and splitting
* replace hard coded opcodes with major opcodes
* replace hard coded opcodes with major opcodes
* add asserts and fix reg numbering
* add asserts and fix reg numbering
* minor updates
* revert changes
* remove constant pool from encoder TODO: add flag for JIT
* extend test cases
* minor fixes
* minor fixes
* update float test case
* stringHash fix on x64
* remove conditional ConstantPool write
* brainfuck minor fixes
* minor arm fixes
* split fix
* brainfuck and fib
* brain fuck
* arg_count, person
* add ignore
* typo
* riscv test sieve attempt
* minor changes
* riscv5 emulator additions
* arm eval setup
* Update riscv.java
* arm eval basics
* delta fixes
* arm fixes
* testfib arm
* arg_count
* small update for test newton
* small update for test newton
* testNewton runs on x64, riscv and arm
* arm additions
* arm pc eval fix
* arm workings
* debugging
* Progress sieve on ARM
Most ops need WMASK as the output, to exclude RSP.
calloc sentinal changes to multiple of 4
NewArm needs to set arg X0 to #1; arg X1 is length.
Fix EvalARM calling calloc & not advancing PC.
Fix EvalARM using ints vs longs.
Fix EvalARM missing AndI encoding.
* Fix some arm encoding
Fix some OBOB in R5 calloc encoding.
Sort EvalArm by major opcodes.
Add ASL. Remove leading switch. Fix OBOB in calloc.
Fix shift in ld/st with reg+offset
* arm sieve test
* test person push
* brainFuck arm
* "and" "or" syntactic sugar
* update encoding
* ch23 `and` `or`
* hack parse trinary for and, or
* close
* fixed or issue
* Update CallEndNode.java
* fix type issue
* fixed
* Adjust parseTrinary precedence vs && ||
* Fix arm simulation return
* Formatting
* Formatting
* simplify rn to be always 0.
* ch24 init
* stacked rel
* stack init
* stack rel
* remove parenthesis
* got rid of old test case
* update
* upgrade eval
* arm encoding bugs
encodeing cset had a shift wrong
eval missed using 0 for r31
* remove debug prints
* force main to encode first
* fix for missing main
* got rid of debug prints
* backwards with ch23
* simple new test cases
* update test cases
* enable old test
* got rid of own test case
* fix test11
* inline Api
* inline x86_64
* inline test cases
* fix stacked_r_5
* got rid of redundant rdid -1 set
* Several new fuzzer addDeps/keep bugs.
Fix risc/arm spill code values for passing 20 args.
* Update README
Move ch23_ch24 branch into ROADMAP
* Create TypeAnalysis.md
* Update TypeAnalysis.md
* Update TypeAnalysis.md
* More lattices for main
* Update TypeAnalysis.md
* Update TypeAnalysis.md
* TypeAnalysis continued
* fix typos
* pointers
* typo fix in reader
* Update TypeAnalysis.md
* sccp first attempt
* test
* init
* still debug
* Update TypeAnalysis.md
* more examples
* More docs
* Update TypeAnalysis.md
* widen phi nodes in loops
* extra debug stuff for opto
* Work in progress opto pass
* Progress on opto
* opto missing deps
ConFldOff needs String.equals in `eq`
Fix monotonic xfer functions in
- CallENd, CProj, Load, Arith
Mostly if either TOP or BOT inputs, the output is the matching TOP or BOT
* push mid-progress
* progress sccp
* Make all the default parser integer types pre-widen
Function sigs to calls allow wide ints
* progress sccp
* Update TypeInteger.java
* progress SCCP
* Progress SCCP
* Progress SCCP
A series of minor fixes, generally making transfer functions monotonic, or p[reserving sanity for error test cases.
* Progress on opto
Most tests pass, a few failures remain.
Split Opto code into a seperate file.
Improve `compute` precision in several places showing up during opto.
bugfix: "split-thru-phis" on Parms changes calling conventions. Not ready for that yet.
* most tests pass
Handle non-default main.
Simplify trivial inlining cutout test.
ParmNode excludes most Phi opts
Region idom excludes dead paths
RPC now interns
* Fix arm NOT encoding
* all tests pass
Float math handles high types monotonically
Minus node does not reset int widen.
Phi widen handles non-int mintype
Dead returns do not error complain.
Better handling default vs dead main
* If NewNode is high, produce high results
* BrainFuck uses a string
* README
* Update README.md
* Typos from copilot review
* monotonic fix MinusF
* Update TypeAnalysis.md
* Update TypeInteger.java
---------
Co-authored-by: Hadházy Tamás <helsgithub15@gmail.com>
Co-authored-by: Tamás Hadházy <85063808+Hels15@users.noreply.github.com>
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