More test case vs RA cleanup

Missing a few risc/arm encodings.
Make private many tests, so they don't escape and the escaped fcn inflate x86 spill numbers

5 files changed, 11 insertions, 6 deletions

diff --git a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java
index 4fbd6840..53494092 100644
--- a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java
+++ b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java
@@ -17,7 +17,7 @@ public class LoadARM extends MemOpARM {
         super(ld, base, idx, off, 0);
     }
     @Override public String op() { return "ld"+_sz; }
-    @Override public RegMask outregmap() { return size() >= 4 ? arm.MEM_MASK : arm.RMASK; }
+    @Override public RegMask outregmap() { return size() >= 4 ? arm.MEM_MASK : arm.WMASK; }
 
     private static final int[] OP_LOADS  = new int[]{ Arm64.OP_LOAD_IMM_8,  Arm64.OP_LOAD_IMM_16,  Arm64.OP_LOAD_IMM_32,  Arm64.OP_LOAD_IMM_64, };
 
diff --git a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java
index ac21c706..f8e450f6 100644
--- a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java
+++ b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java
@@ -18,9 +18,9 @@ public class NotARM extends MachConcreteNode implements MachNode{
         // subtracting zero from rs will just yield rs, it sets the zero flag and then it's used in cset
         short self = enc.reg(this );
         short reg1 = enc.reg(in(1));
-        int subs = Arm64.imm_inst(Arm64.OP_SUBS, 0, reg1, self);
+        int subs = Arm64.imm_inst(Arm64.OP_SUBS, 0, reg1, 31);
         enc.add4(subs);
-        int cset = Arm64.cond_set(Arm64.OP_CSET, 31, Arm64.COND.EQ, 31, reg1);
+        int cset = Arm64.cset(Arm64.OP_CSET, 31, Arm64.COND.EQ, 31, self);
         enc.add4(cset);
     }
 
diff --git a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java
index dbe9ceb0..6f499db1 100644
--- a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java
+++ b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java
@@ -15,7 +15,8 @@ public class NotRISC extends MachConcreteNode implements MachNode {
     @Override public void encoding( Encoding enc ) {
         short dst = enc.reg(this );
         short src = enc.reg(in(1));
-        enc.add4(RiscV.i_type(RiscV.OP_IMM, dst, 2, src, 1));
+        // SEQZ is unsigned: negative nonzero inputs must also produce false.
+        enc.add4(RiscV.i_type(RiscV.OP_IMM, dst, 3, src, 1));
     }
     @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)); }
 }
diff --git a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java
index 690e2102..9bc86565 100644
--- a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java
+++ b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java
@@ -7,7 +7,11 @@ import com.seaofnodes.simple.node.Node;
 public class SetIRISC extends ImmRISC {
     final boolean _unsigned;    // slti vs sltiu
     public SetIRISC( Node src, int imm12, boolean unsigned ) {
-        super(src,imm12);
+        this(src,imm12,unsigned,true);
+    }
+    public SetIRISC( Node src, int imm12, boolean unsigned, boolean pop ) {
+        super(src,imm12,pop);
+        if( !pop ) _inputs.setLen(2);
         _unsigned = unsigned;
     }
     @Override public String op() { return "slt" + (_unsigned ? "u":"") + "i"; }
diff --git a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
index ae69b439..19b91866 100644
--- a/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
+++ b/chapter25/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -317,7 +317,7 @@ public class riscv extends Machine {
         // x <= y - flip and negate; !(y < x); `slt tmp=y,x; xori dst=tmp,#1`
         case "<=" -> new XorIRISC(new SetRISC(bool.swap12(), false),1,false);
         // x == y - sub and vs0 == `sub tmp=x-y; sltu dst=tmp,#1`
-        case "==" -> new SetIRISC(new SubRISC(bool),1,true);
+        case "==" -> new SetIRISC(new SubRISC(bool),1,true,false);
         default -> throw Utils.TODO();
         };
     }