Add back copy coaleascing in ch21

Minor arm encoding fix.

3 files changed, 34 insertions, 3 deletions

diff --git a/chapter25/src/test/java/com/seaofnodes/simple/Chapter20Test.java b/chapter25/src/test/java/com/seaofnodes/simple/Chapter20Test.java
index 43112594..20619c1b 100644
--- a/chapter25/src/test/java/com/seaofnodes/simple/Chapter20Test.java
+++ b/chapter25/src/test/java/com/seaofnodes/simple/Chapter20Test.java
@@ -6,6 +6,23 @@ import org.junit.Test;
 import static org.junit.Assert.*;
 
 public class Chapter20Test {
+    @Test public void testInlinedReturnValue() {
+        String src = """
+struct S { int x; };
+val f = { S s -> s.x = g(); };
+val g = { -> 123; };
+S !s = new S;
+return f(s);
+""";
+        // The entry of g can disappear before its Return is folded into f.
+        // Exercise both worklist orders; deleting the entry does not kill 123.
+        for( int seed=0; seed<64; seed++ ) {
+            CodeGen code = new CodeGen(src,seed,true).parse().opto().typeCheck();
+            assertEquals("seed "+seed, "123", Eval2.eval(code,0));
+        }
+    }
+
+
     @Test public void testPrintingRegisters() throws Exception {
         com.seaofnodes.simple.codegen.PrintRegTestSupport.check();
     }
diff --git a/chapter25/src/test/java/com/seaofnodes/simple/Chapter21Test.java b/chapter25/src/test/java/com/seaofnodes/simple/Chapter21Test.java
index 6d64f2d2..e8a9e700 100644
--- a/chapter25/src/test/java/com/seaofnodes/simple/Chapter21Test.java
+++ b/chapter25/src/test/java/com/seaofnodes/simple/Chapter21Test.java
@@ -9,6 +9,20 @@ import org.junit.Test;
 import static org.junit.Assert.*;
 
 public class Chapter21Test {
+    @Test public void testArmSubtractRegisters() {
+        EvalArm64 cpu = new EvalArm64(new byte[16],16);
+        cpu.st4(0,0xCB020020); // SUB X0,X1,X2, no shift or flag update.
+        for( long[] pair : new long[][]{{7,3},{3,7},{Long.MIN_VALUE,1},{1L<<40,3}} ) {
+            cpu._pc = 0;
+            cpu.regs[1] = pair[0]; cpu.regs[2] = pair[1];
+            cpu.N=true; cpu.Z=false; cpu.C=true; cpu.V=true;
+            assertEquals(0,cpu.step(1));
+            assertEquals(pair[0]-pair[1],cpu.regs[0]);
+            assertTrue(cpu.N); assertFalse(cpu.Z); assertTrue(cpu.C); assertTrue(cpu.V);
+        }
+    }
+
+
     @Test public void testRisc64BitStore() {
         byte[] mem = new byte[24];
         EvalRisc5 cpu = new EvalRisc5(mem,mem.length);
diff --git a/chapter25/src/test/java/com/seaofnodes/simple/EvalArm64.java b/chapter25/src/test/java/com/seaofnodes/simple/EvalArm64.java
index d511f18f..89e09f69 100644
--- a/chapter25/src/test/java/com/seaofnodes/simple/EvalArm64.java
+++ b/chapter25/src/test/java/com/seaofnodes/simple/EvalArm64.java
@@ -287,13 +287,13 @@ public class EvalArm64 {
                 break;
             }
 
-            case 0x8B: {
-                // add(shifted register)
+            case 0x8B, 0xCB: {
+                // add/sub(register), unshifted form emitted by Simple
                 int rn = (ir >> 5)  & 0x1F;
                 int rm = (ir >> 16) & 0x1F;
                 long lhs = regs[rn];
                 long rhs = regs[rm];
-                rval = lhs + rhs;
+                rval = opcode1==0x8B ? lhs + rhs : lhs - rhs;
                 break;
             }