More test case vs RA cleanup

Missing a few risc/arm encodings.
Make private many tests, so they don't escape and the escaped fcn inflate x86 spill numbers

2 files changed, 28 insertions, 5 deletions

diff --git a/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java b/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java
index 2fa4aec1..1ff77f59 100644
--- a/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java
+++ b/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java
@@ -329,6 +329,11 @@ public class EvalArm64 {
                 rval = regs[rn] & immediate;
                 break;
             }
+            case 0xB2: { // ORR (immediate)
+                int rn = (ir >>> 5) & 31;
+                rval = (rn==31 ? 0 : regs[rn]) | Arm64.decodeImm12((ir >>> 10) & 0x1FFF);
+                break;
+            }
             case 0x93, 0xD3: { // SBFM/UBFM: shifts and signed/unsigned extracts
                 int immr = (ir >>> 16) & 63;
                 int imms = (ir >>> 10) & 63;
@@ -372,6 +377,12 @@ public class EvalArm64 {
             }
 
             case 0x9A: {
+                if( (ir & 0xFFE0FC00)==0x9AC00C00 ) { // SDIV Xd,Xn,Xm
+                    int rn=(ir >>> 5)&31, rm=(ir >>> 16)&31;
+                    long lhs=rn==31 ? 0 : regs[rn], rhs=rm==31 ? 0 : regs[rm];
+                    rval = rhs==0 ? 0 : lhs/rhs;
+                    break;
+                }
                 int encodedCond = (ir >> 12) & 0xF;
                 int decodedCond  = encodedCond ^ 1;
                 // conditional select(csel)
@@ -394,7 +405,7 @@ public class EvalArm64 {
                 case 0xF -> false          ;   // never
                 default -> throw new UnsupportedOperationException();
                 };
-                if( cond ) rval = 1;
+                rval = cond ? 1 : 0;
                 break;
             }
             case 0x9B: {       // mul
@@ -761,7 +772,8 @@ public class EvalArm64 {
             }
             if(rdid != -1) {
                 if(is_f) fregs[rdid] = frval;
-                else      regs[rdid] =  rval;
+                // Register 31 is XZR except for ADD/SUB immediate, which writes SP.
+                else if( rdid!=31 || opcode1==0x91 || opcode1==0xD1 ) regs[rdid] = rval;
             }
 
             pc += 4;
diff --git a/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalRisc5.java b/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalRisc5.java
index 46baf447..e6860ccd 100644
--- a/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalRisc5.java
+++ b/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalRisc5.java
@@ -203,6 +203,17 @@ public class EvalRisc5 {
                 break;
             }
 
+            case 0x27: { // FSW/FSD
+                int rs1=(int)regs[(ir >>> 15)&31], rs2=(ir >>> 20)&31;
+                int addr=rs1+((ir >> 25)<<5)+((ir >>> 7)&31);
+                switch((ir >>> 12)&7) {
+                case 2: st4(addr,Float.floatToRawIntBits((float)fregs[rs2])); break;
+                case 3: st8(addr,Double.doubleToRawLongBits(fregs[rs2])); break;
+                default: trap=3;
+                }
+                rdid=0;
+                break;
+            }
             case 0x23: { // Store 0b0100011
                 int  rs1 = (int)regs[(ir >> 15) & 0x1f]; // Address chop to 32b
                 long rs2 = regs[(ir >> 20) & 0x1f];
@@ -252,7 +263,7 @@ public class EvalRisc5 {
                     case 0 -> (is_reg && (ir & 0x40000000) != 0) ? (rs1 - rs2) : (rs1 + rs2);
                     case 1 -> rs1 << (rs2 & 0x3F);
                     case 2 -> (rs1 < rs2) ? 1 : 0;
-                    case 3 -> (rs1 < rs2) ? 1 : 0;
+                    case 3 -> Long.compareUnsigned(rs1,rs2)<0 ? 1 : 0;
                     case 4 -> rs1 ^ rs2;
                     case 5 -> (ir & 0x40000000) != 0 ? (rs1 >> (rs2 & 0x3F)) : (rs1 >>> (rs2 & 0x3F));
                     case 6 -> rs1 | rs2;
@@ -329,8 +340,8 @@ public class EvalRisc5 {
                     is_f = false; // Output into a GPR
                     rval = switch( (ir >> 12) & 7 ) {
                     case 0 -> lhs <= rhs ? 1 : 0;
-                    case 1 -> lhs == rhs ? 1 : 0;
-                    case 2 -> lhs <  rhs ? 1 : 0;
+                    case 1 -> lhs <  rhs ? 1 : 0;
+                    case 2 -> lhs == rhs ? 1 : 0;
                     default -> throw new UnsupportedOperationException();
                     };
                     break;