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| -rw-r--r-- | chapter19/README.md | 22 | ||||
| -rw-r--r-- | chapter20/README.md | 4 | ||||
| -rw-r--r-- | chapter21/README.md | 18 |
3 files changed, 28 insertions, 16 deletions
diff --git a/chapter19/README.md b/chapter19/README.md index 752e139f..0d8e481f 100644 --- a/chapter19/README.md +++ b/chapter19/README.md @@ -38,8 +38,8 @@ implementation at least the ability to add CPU ports lazily. ## Machine Specific Nodes -We add a notion of "machine specific" Nodes, which implement the `Mach` -interface. `Mach` nodes define incoming and outgoing registers for every +We add a notion of "machine specific" Nodes, which implement the `MachNode` +interface. `MachNode` nodes define incoming and outgoing registers for every instruction, their bit encodings and user representations. Later we'll add function unit information for a better local schedule. @@ -124,11 +124,11 @@ E.g `lea` is not present. ### Branching -In `x86_64_v2`, branching requires a comparison instruction to set flags, -followed by a jump instruction that uses those flags. -In contrast, RISC-V includes all necessary operands within the -branch instruction itself, eliminating the need for a separate -comparison step. + +In `x86_64_v2`, branching requires a comparison instruction to set flags, +followed by a jump instruction that uses those flags. In contrast, RISC-V +includes all necessary operands within the branch instruction itself, +eliminating the need for a separate comparison step. E.g ``` @@ -136,9 +136,10 @@ beq x10, x11, some_label ``` `CBranchRISC` implements this behavior. + ### No R-Flags -No R-flags exist in RiSC-V. To obtain similar functionality: +No R-flags exist in RiSC-V. To obtain similar functionality: We can set the value of registers based on the result of the comparison this way explicitly. ``` xor a0, a0, a1 @@ -149,8 +150,9 @@ The `seqz` instruction will set `a0` to 1 if `a0` is zero from the previous oper This matches `SetRISC` in the `nodes/cpus/riscv` port. ### Fixed instruction length -RISC-V instructions have fixed length of 32 bits(in most cases) which means that we can benefit -from displacements in the encoding side. + +RISC-V instructions have fixed length of 32 bits(in most cases) which means +that we can benefit from displacements in the encoding side. E.g ``` diff --git a/chapter20/README.md b/chapter20/README.md index 06bc481f..ab1d9ca4 100644 --- a/chapter20/README.md +++ b/chapter20/README.md @@ -88,8 +88,8 @@ Coloring proceeds in rounds until we get a coloring: also have a set of reaching defs per-block. - Color the interference graph. Nodes (live ranges) in the graph which are - strictly low degree (more available registers than neighbors) will guaranteed - get a color. These can be removed from the graph - since they will + strictly low degree (more available registers than neighbors) are guaranteed + to get a color. These can be removed from the graph - since they will guaranteed get a register (color) because they have so few conflicting neighbors. Removing these trivial nodes makes more nodes go trivial, and this process repeats until either we run out (and are guaranteed a coloring) diff --git a/chapter21/README.md b/chapter21/README.md index 2fa813a4..d5077488 100644 --- a/chapter21/README.md +++ b/chapter21/README.md @@ -13,6 +13,15 @@ bugs linger until we can actually run the code. This means that other chapters have updates and bug-fixes to the work being described here. +Encodings are an entirely bit-picky nit-picky affair. There's no real rocket +science here, but instead there's an boundless opportunity for off-by-1 errors. +If you find a bug here, do not be surprised! Its almost surely a "shallow" +bug... and there's bound to be a few until Simple gets more programmer hours +under its belt. + + + +You can also read [this chapter](https://github.com/SeaOfNodes/Simple/tree/linear-chapter21) in a linear Git revision history on the [linear](https://github.com/SeaOfNodes/Simple/tree/linear) branch and [compare](https://github.com/SeaOfNodes/Simple/compare/linear-chapter20...linear-chapter21) it to the previous chapter. # Table of Contents @@ -20,7 +29,7 @@ described here. 2. [Infrastructure](#infrastructure) 3. [AMD64](#amd64) - [REX PREFIX](#rex-prefix) - - [LARGE CONSTANT](#large-constants) + - [Large constants](#large-constants) - [MODR/M](#modrm) - [SIB](#sib) - [Displacement](#displacement) @@ -47,9 +56,9 @@ described here. 5. [RISCV](#riscv) - [Instruction formats](#instruction-formats) - - [FLOAT](#float) + - [Float](#float) - [Indirect](#indirectmemop-2) - - [BRANCH](#branch) + - [Branch](#branch) - [Function Constant](#function-constant) - [LUI](#lui) - [Large constants](#large-constants) @@ -74,7 +83,7 @@ For *x86-64(amd64):*, we use the latest Intel manual for the [encoding rules](ht For *riscv* we currently target [RVA23U64](https://msyksphinz-self.github.io/riscv-isadoc/html/). ### ARMV8/AArch64 : -For *arm*(aarch64) we use this collection for the [encoding rules](https://docsmirror.github.io/A64/2023-06/index.html). +For *arm*(aarch64) we use this collection for the [encoding rules](https://docsmirror.github.io/A64/20a23-06/index.html). *Note*: We only support 64 bits ARM encodings. --- @@ -112,6 +121,7 @@ On *RISC-V*, where the documentation provides big-endian encodings, this function also converts them to little-endian. For other architectures, no conversion is necessary. ## Endianness + ARM, RISC-V, and x86 are all little-endian architectures in practice, meaning the least significant byte is stored first. We ensure that instruction encodings are generated in little-endian format accordingly. |