diff options
Diffstat (limited to 'chapter21/src/main/java/com')
16 files changed, 23 insertions, 30 deletions
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddIRISC.java index eb02a63d..a85ce5d0 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddIRISC.java @@ -8,7 +8,7 @@ public class AddIRISC extends ImmRISC { public AddIRISC( Node add, int imm12, boolean pop ) { super(add,imm12,pop); } @Override public String op() { return "addi"; } @Override public String glabel() { return "+"; } - @Override int opcode() { return riscv.I_TYPE; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() {return 0;} @Override public AddIRISC copy() { // Clone the AddI, using the same inputs-only code used during inst select. diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndIRISC.java index 3526df61..9887b735 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndIRISC.java @@ -7,6 +7,6 @@ public class AndIRISC extends ImmRISC { AndIRISC( Node and, int imm) { super(and,imm); } @Override public String op() { return "andi"; } @Override public String glabel() { return "&"; } - @Override int opcode() { return riscv.I_TYPE; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() {return 7;} } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java index ec500aa7..ce478761 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java @@ -32,7 +32,7 @@ public class CallRISC extends CallNode implements MachNode, RIPRelSize { // Long form: auipc rX,imm20/32; jal r0,[rX+imm12/32] enc.relo(this); short rpc = enc.reg(this); - enc.add4(riscv.j_type(riscv.J_JAL, rpc, 0)); + enc.add4(riscv.j_type(riscv.OP_JAL, rpc, 0)); } // Delta is from opcode start @@ -46,7 +46,7 @@ public class CallRISC extends CallNode implements MachNode, RIPRelSize { @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { short rpc = enc.reg(this); if( opLen==4 ) { - enc.patch4(opStart,riscv.j_type(riscv.J_JAL, rpc, delta)); + enc.patch4(opStart,riscv.j_type(riscv.OP_JAL, rpc, delta)); } else { throw Utils.TODO(); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java index c2947bc1..2afbbfa9 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java @@ -18,7 +18,7 @@ public class CallRRISC extends CallNode implements MachNode { @Override public void encoding( Encoding enc ) { short rpc = enc.reg(this); short src = enc.reg(in(_inputs._len-1)); - int body = riscv.i_type(riscv.OP_CALL, rpc, 0, src, 0); + int body = riscv.i_type(riscv.OP_JALR, rpc, 0, src, 0); enc.add4(body); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java index 2831360d..3fa6862a 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java @@ -27,7 +27,7 @@ public class FunRISC extends FunNode implements MachNode { _maxArgSlot = riscv.maxSlot(enc._fun.sig()); _frameAdjust = (short) (_maxSlot+1 - _maxArgSlot); if( _frameAdjust == 0 ) return; // Skip if no frame adjust - enc.add4(riscv.i_type(riscv.I_TYPE, riscv.SP, 0, riscv.SP, (_frameAdjust*8) & 0xFFF)); + enc.add4(riscv.i_type(riscv.OP_IMM, riscv.SP, 0, riscv.SP, (_frameAdjust*8) & 0xFFF)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java index fbe8c984..764c49e6 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java @@ -20,7 +20,7 @@ public class IntRISC extends ConstantNode implements MachNode { TypeInteger ti = (TypeInteger)_con; // Explicit truncation of larger immediates; this will sign-extend on // load and this is handled during instruction selection. - enc.add4(riscv.i_type(riscv.I_TYPE, dst, 0, riscv.ZERO, (int)(ti.value() & 0xFFF))); + enc.add4(riscv.i_type(riscv.OP_IMM, dst, 0, riscv.ZERO, (int)(ti.value() & 0xFFF))); } @Override public void asm(CodeGen code, SB sb) { String reg = code.reg(this); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java index 8d84a012..1639811c 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java @@ -23,7 +23,7 @@ public class NewRISC extends NewNode implements MachNode { // A1 is a caller-save, allowed to crush building external address // auipc enc.add4(riscv.u_type(riscv.OP_AUIPC, riscv.A1, 0)); - enc.add4(riscv.i_type(riscv.OP_CALL, riscv.RPC, 0, riscv.A1, 0)); + enc.add4(riscv.i_type(riscv.OP_JALR, riscv.RPC, 0, riscv.A1, 0)); } // General form: "alloc #bytes PC" diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrIRISC.java index 70cd9c48..d6c32fec 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrIRISC.java @@ -5,7 +5,7 @@ import com.seaofnodes.simple.node.Node; public class OrIRISC extends ImmRISC { OrIRISC( Node and, int imm) { super(and,imm); } - @Override int opcode() { return riscv.I_TYPE; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() { return 6; } @Override public String glabel() { return "|"; } @Override public String op() { return "ori"; } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java index 87927242..aa1d99e9 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java @@ -27,9 +27,9 @@ public class RetRISC extends ReturnNode implements MachNode { @Override public void encoding( Encoding enc ) { int frameAdjust = fun()._frameAdjust; if( frameAdjust > 0 ) - enc.add4(riscv.i_type(riscv.I_TYPE, riscv.SP, 0, riscv.SP, (frameAdjust*-8) & 0xFFF)); + enc.add4(riscv.i_type(riscv.OP_IMM, riscv.SP, 0, riscv.SP, (frameAdjust*-8) & 0xFFF)); short rpc = enc.reg(rpc()); - enc.add4(riscv.i_type(riscv.OP_CALL, riscv.ZERO, 0, rpc, 0)); + enc.add4(riscv.i_type(riscv.OP_JALR, riscv.ZERO, 0, rpc, 0)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllIRISC.java index dedbf783..2ec657ae 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllIRISC.java @@ -5,7 +5,7 @@ import com.seaofnodes.simple.node.Node; public class SllIRISC extends ImmRISC { SllIRISC( Node and, int imm) { super(and,imm); } - @Override int opcode() { return riscv.I_TYPE; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() { return 1; } @Override public String glabel() { return "<<"; } @Override public String op() { return "slli"; } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java index 94270f3a..081b4fe0 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java @@ -5,7 +5,7 @@ import com.seaofnodes.simple.node.Node; public class SraIRISC extends ImmRISC { SraIRISC( Node and, int imm) { super(and,imm); } - @Override int opcode() { return riscv.I_TYPE; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() { return 5;} @Override public String glabel() { return ">>"; } @Override public String op() { return "srai"; } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlIRISC.java index 078a2fca..472ac8b3 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlIRISC.java @@ -5,7 +5,7 @@ import com.seaofnodes.simple.node.Node; public class SrlIRISC extends ImmRISC { SrlIRISC( Node and, int imm, boolean pop) { super(and,imm,pop); } - @Override int opcode() { return riscv.I_TYPE; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() { return 5; } @Override public String glabel() { return ">>>"; } @Override public String op() { return "srli"; } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java index d971bf33..17613009 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java @@ -21,7 +21,7 @@ public class TFPRISC extends ConstantNode implements MachNode, RIPRelSize { // auipc t0,0 int auipc = riscv.u_type(riscv.OP_AUIPC, dst, 0); // addi t1,t0 + #0 - int addi = riscv.i_type(riscv.I_TYPE, dst, 0, dst, 0); + int addi = riscv.i_type(riscv.OP_IMM, dst, 0, dst, 0); enc.add4(auipc); enc.add4(addi); } @@ -40,7 +40,7 @@ public class TFPRISC extends ConstantNode implements MachNode, RIPRelSize { int next = opStart + opLen; enc.patch4(opStart,riscv.u_type(riscv.OP_AUIPC, rpc, delta)); // addi(low 12 bits) - enc.patch4(next,riscv.i_type(riscv.I_TYPE, rpc, 0, rpc, delta & 0xFFF)); + enc.patch4(next,riscv.i_type(riscv.OP_IMM, rpc, 0, rpc, delta & 0xFFF)); // addi } else { // should not happen as one instruction is 4 byte, and TFP arm encodes 2. diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/UJmpRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/UJmpRISC.java index 29e1440c..84224a01 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/UJmpRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/UJmpRISC.java @@ -22,7 +22,7 @@ public class UJmpRISC extends CFGNode implements MachNode, RIPRelSize { // Short form +/-4K: beq r0,r0,imm12 // Long form: auipc rX,imm20/32; jal r0,[rX+imm12/32] enc.jump(this,uctrl()); - enc.add4(riscv.j_type(riscv.J_JAL, 0, 0)); + enc.add4(riscv.j_type(riscv.OP_JAL, 0, 0)); } // Delta is from opcode start @@ -35,7 +35,7 @@ public class UJmpRISC extends CFGNode implements MachNode, RIPRelSize { // Delta is from opcode start @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { if( opLen==4 ) { - enc.patch4(opStart,riscv.j_type(riscv.J_JAL, 0, delta)); + enc.patch4(opStart,riscv.j_type(riscv.OP_JAL, 0, delta)); } else { throw Utils.TODO(); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorIRISC.java index 5842f04d..e91ffb9e 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorIRISC.java @@ -5,7 +5,7 @@ import com.seaofnodes.simple.node.Node; public class XorIRISC extends ImmRISC { XorIRISC( Node and, int imm) { super(and,imm); } - @Override int opcode() { return riscv.I_TYPE; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() { return 4; } @Override public String glabel() { return "^"; } @Override public String op() { return "xori"; } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java index 9ac6fe79..421c91e9 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java @@ -106,6 +106,7 @@ public class riscv extends Machine { public static int OP_LOAD = 0b00_000_11; public static int OP_LOADFP = 0b00_001_11; public static int OP_CUSTOM0 = 0b00_010_11; + public static int OP_IMM = 0b00_100_11; public static int OP_AUIPC = 0b00_101_11; public static int OP_STORE = 0b01_000_11; @@ -118,17 +119,9 @@ public class riscv extends Machine { public static int OP_FP = 0b10_100_11; public static int OP_BRANCH = 0b11_000_11; + public static int OP_JALR = 0b11_001_11; public static int OP_RESERVED= 0b11_010_11; - - public static int OP_CALL = 0b11_001_11; - - - - //I_type opcode: 0010 0011 - public static int I_TYPE = 0x13; - - // 0110 0111 - public static int J_JAL = 0b1101111; + public static int OP_JAL = 0b11_011_11; // Since riscv instructions are fixed we can just or them togehter @@ -171,7 +164,7 @@ public class riscv extends Machine { int imm11 = (delta>>11) & 1; int imm12_19 = (delta>>12) & 0xFF; int imm20 = (delta>>19) & 1; - int bits = imm20<<20 | imm12_19 << 12 | imm11 << 11 | imm10_01; + int bits = imm20<<19 | imm10_01 << 9 | imm11 << 8 | imm12_19; return bits << 12 | rd << 7 | opcode; } |