diff options
Diffstat (limited to 'chapter21/src/main/java/com')
9 files changed, 11 insertions, 10 deletions
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java index ef3c4fc8..d07c5cef 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java @@ -28,7 +28,6 @@ public class BranchARM extends IfNode implements MachNode, RIPRelSize { @Override public RegMask outregmap() { return null; } @Override public void invert() { _bop = invert(_bop); } - // Encoding is appended into the byte array; size is returned @Override public void encoding( Encoding enc ) { // Assuming that condition flags are already set. These flags are set // by comparison (or sub). No need for regs because it uses flags diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java index fe36390c..c0193323 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java @@ -5,7 +5,7 @@ import com.seaofnodes.simple.codegen.*; import com.seaofnodes.simple.node.*; // Compare with immediate. -// Conditional compare (immediate)? e.g CCMP(immediate) +// CMP (immediate) - SUBS public class CmpIARM extends MachConcreteNode implements MachNode { final int _imm; final String _bop; @@ -27,7 +27,7 @@ public class CmpIARM extends MachConcreteNode implements MachNode { @Override public RegMask outregmap() { return arm.FLAGS_MASK; } @Override public boolean isClone() { return true; } @Override public Node copy() { return new CmpIARM(this); } - // Encoding is appended into the byte array; size is returned + @Override public void encoding( Encoding enc ) { arm.imm_inst(enc,in(1),in(1), arm.OPI_CMP,_imm); } // General form: "cmp rs1, 1" diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java index 03a78c5e..a78312fa 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java @@ -19,7 +19,6 @@ public class SetARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { assert i==1; return arm.FLAGS_MASK; } @Override public RegMask outregmap() { return arm.RMASK; } - // Encoding is appended into the byte array; size is returned @Override public void encoding( Encoding enc ) { int body = arm.cset(arm.OP_CSET,0b11111, arm.make_condition(_bop), 0b0111111, enc.reg(this)); enc.add4(body); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java index de8048a6..a92b4e21 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java @@ -33,10 +33,11 @@ public abstract class MemOpRISC extends MemOpNode implements MachNode { int func3 = -1; // no unsigned flavour for store, so both signed and unsigned trigger the same if(this instanceof StoreRISC) { - if( _declaredType == TypeInteger. I8 || _declaredType == TypeInteger.U8) func3=0; // SB + if( _declaredType == TypeInteger. I8 || _declaredType == TypeInteger.U8 || _declaredType == TypeInteger.BOOL) func3=0; // SB if( _declaredType == TypeInteger.I16 || _declaredType == TypeInteger.U16 ) func3=1; // SH - if( _declaredType == TypeInteger.I32 || _declaredType == TypeInteger.U32) func3=2; // SW + if( _declaredType == TypeInteger.I32 || _declaredType == TypeInteger.U32 || _declaredType instanceof TypeMemPtr) func3=2; // SW if( _declaredType == TypeInteger.BOT ) func3=3; // SD + if( func3 == -1 ) throw Utils.TODO(); return func3; } if( _declaredType == TypeInteger. I8 ) func3=0; // LB @@ -47,6 +48,7 @@ public abstract class MemOpRISC extends MemOpNode implements MachNode { if( _declaredType == TypeInteger.BOOL) func3=4; // LBU if( _declaredType == TypeInteger.U16 ) func3=5; // LHU if( _declaredType == TypeInteger.U32 ) func3=6; // LWU + // float if(_declaredType == TypeFloat.F32) func3 = 2; // fLW fSW if(_declaredType == TypeFloat.F64) func3 = 3; // fLD fSD diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java index 1639811c..dfa40cad 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java @@ -16,7 +16,6 @@ public class NewRISC extends NewNode implements MachNode { @Override public RegMask outregmap() { return null; } @Override public RegMask killmap() { return riscv.riscCallerSave(); } - // Encoding is appended into the byte array; size is returned @Override public void encoding( Encoding enc ) { // Generic external encoding; 2 ops. enc.external(this,"calloc"); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java index cca0327c..2a53559f 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java @@ -10,7 +10,7 @@ public class NotRISC extends ImmRISC { @Override public RegMask outregmap() { return riscv.RMASK; } @Override public String op() { return "not"; } // sltiu: x <u 1 ? 1 : 0; only zero is unsigned-less-than 1 - @Override int opcode() { return 19; } + @Override int opcode() { return riscv.OP_IMM; } @Override int func3() { return 2; } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)); } } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java index 8cec13f9..f270bf12 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java @@ -13,5 +13,5 @@ public class SetIRISC extends ImmRISC { @Override public String op() { return "slt" + (_unsigned ? "u":"") + "i"; } @Override public String glabel() { return "<"+ (_unsigned ? "u":""); } @Override int opcode() { return 0b0010011; } - @Override int func3() { return _unsigned ? 0b011 : 0x010; } + @Override int func3() { return _unsigned ? 0b011 : 0b010; } } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java index 2cd1bac0..636c5a5f 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java @@ -17,4 +17,4 @@ public class SetRISC extends MachConcreteNode implements MachNode { @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" < ").p(code.reg(in(2))); } -} +}
\ No newline at end of file diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java index ae43ab55..a97c6d10 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java @@ -181,6 +181,8 @@ public class riscv extends Machine { public static int s_type(int opcode, int func3, int rs1, int rs2, int imm12) { assert 0 <= rs1 && rs1 < 32; assert 0 <= rs2 && rs2 < 32; + assert 0 <= func3; + assert imm12 >= 0; // Masked to high zero bits by caller int imm_lo = imm12 & 0x1F; int imm_hi = imm12 >> 5; |