diff options
Diffstat (limited to 'chapter21/src/main')
53 files changed, 199 insertions, 94 deletions
diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddARM.java index a65b9553..205ab6e4 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddARM.java @@ -11,7 +11,7 @@ public class AddARM extends MachConcreteNode implements MachNode { @Override public RegMask outregmap() { return arm.RMASK; } // ADD (shifted register) - @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,0b10001011); } + @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,arm.OP_ADD); } // General form: "rd = rs1 + rs2" @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" + ").p(code.reg(in(2))); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddFARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddFARM.java index 6e1930ed..e429a967 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddFARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddFARM.java @@ -11,7 +11,7 @@ public class AddFARM extends MachConcreteNode implements MachNode { @Override public RegMask outregmap() { return arm.DMASK; } //FADD (scalar) - @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,0b00011110); } + @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,arm.OPF_ADD); } // Default on double precision for now(64 bits) // General form: "addf rd = src1 + src2 diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddIARM.java index 443320f0..3a3e78d4 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddIARM.java @@ -18,7 +18,7 @@ public class AddIARM extends MachConcreteNode implements MachNode { @Override public RegMask outregmap() { return arm.RMASK; } //ADD (immediate) @Override public void encoding( Encoding enc ) { - arm.imm_inst(enc,this,0b1001000100,_imm); + arm.imm_inst(enc,this,arm.OPI_ADD,_imm); } // General form: "addi rd = rs1 + imm" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndARM.java index c107e87f..d125174b 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndARM.java @@ -13,7 +13,7 @@ public class AndARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } // AND (shifted register) - @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,0b10001010); } + @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,arm.OP_AND); } // General form: #rd = rs1 & rs2 @Override public void asm(CodeGen code, SB sb){ sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" & ").p(code.reg(in(2))); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndIARM.java index 12d7d7c5..e7f45843 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndIARM.java @@ -15,7 +15,7 @@ public class AndIARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } @Override public void encoding( Encoding enc ) { - arm.imm_inst_n(enc,this,0b100100100,_imm); + arm.imm_inst_n(enc,this,arm.OPI_AND,_imm); } // General form: "andi rd = rs1 & imm" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrARM.java index 23776896..b1603338 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrARM.java @@ -10,7 +10,7 @@ public class AsrARM extends MachConcreteNode implements MachNode { @Override public String op() { return "sar"; } @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } - @Override public void encoding( Encoding enc ) { arm.shift_reg(enc,this,0b1010); } + @Override public void encoding( Encoding enc ) { arm.shift_reg(enc,this,arm.OP_ASR); } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" >> ").p(code.reg(in(2))); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrIARM.java index 3371d3d2..eb535201 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrIARM.java @@ -22,7 +22,7 @@ public class AsrIARM extends MachConcreteNode implements MachNode { short rd = enc.reg(this); short rn = enc.reg(in(1)); assert _imm > 0; - enc.add4(arm.imm_shift(0b1001001101,_imm, 0b111111, rn, rd)); + enc.add4(arm.imm_shift(arm.OPI_ASR,_imm, 0b111111, rn, rd)); } // General form: "asri rd = rs1 >> imm" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java index c9f47ba5..e7e7a25b 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java @@ -34,7 +34,7 @@ public class BranchARM extends IfNode implements MachNode, RIPRelSize { // by comparison (or sub). No need for regs because it uses flags enc.jump(this,cproj(0)); // B.cond - enc.add4( arm.b_cond(0b01010100, 0, arm.make_condition(_bop)) ); + enc.add4( arm.b_cond(arm.OP_BRANCH, 0, arm.make_condition(_bop)) ); } // Delta is from opcode start @@ -47,7 +47,7 @@ public class BranchARM extends IfNode implements MachNode, RIPRelSize { // Delta is from opcode start @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { if( opLen==4 ) { - enc.patch4(opStart,arm.b_cond(0b01010100, delta, arm.make_condition(_bop))); + enc.patch4(opStart,arm.b_cond(arm.OP_BRANCH, delta, arm.make_condition(_bop))); } else { throw Utils.TODO(); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java index ed22da06..63d418ff 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java @@ -27,7 +27,7 @@ public class CallARM extends CallNode implements MachNode, RIPRelSize { @Override public void encoding( Encoding enc ) { enc.relo(this); // BL - enc.add4(arm.b(0b100101,0)); // Target patched at link time + enc.add4(arm.b(arm.OP_CALL,0)); // Target patched at link time } // Delta is from opcode start, but X86 measures from the end of the 5-byte encoding @@ -35,7 +35,7 @@ public class CallARM extends CallNode implements MachNode, RIPRelSize { // Delta is from opcode start @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { - enc.patch4(opStart,arm.b(0b100101,delta)); + enc.patch4(opStart,arm.b(arm.OP_CALL,delta)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java index b5c3ecac..b3f55659 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java @@ -19,7 +19,7 @@ public class CallRRARM extends CallNode implements MachNode { // Needs a register, typically a jump-and-link-register opcode // blr short self = enc.reg(this); - enc.add4(arm.blr(0b1101011000111111000000, self)); + enc.add4(arm.blr(arm.OP_CALLRARM, self)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpARM.java index 7b61baf7..8cc4621d 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpARM.java @@ -11,7 +11,7 @@ public class CmpARM extends MachConcreteNode implements MachNode { @Override public RegMask outregmap() { return arm.FLAGS_MASK; } // SUBS (shifted register) - @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,0b11101011); } + @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,arm.OP_CMP); } // General form: "cmp rs1, rs2" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java index be80fb03..1196add9 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java @@ -28,7 +28,7 @@ public class CmpIARM extends MachConcreteNode implements MachNode { @Override public boolean isClone() { return true; } @Override public Node copy() { return new CmpIARM(this); } // Encoding is appended into the byte array; size is returned - @Override public void encoding( Encoding enc ) { arm.imm_inst(enc,this,964,_imm); } + @Override public void encoding( Encoding enc ) { arm.imm_inst(enc,this,arm.OPI_CMP,_imm); } // General form: "cmp rs1, 1" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivARM.java index 4e1f9d5d..8b8af5c3 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivARM.java @@ -10,7 +10,7 @@ public class DivARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } // SDIV - @Override public void encoding( Encoding enc ) { arm.madd(enc,this,0b10011010110,3); } + @Override public void encoding( Encoding enc ) { arm.madd(enc,this,arm.OP_DIV,3); } // General form: "div dst /= src" @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" / ").p(code.reg(in(2))); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivFARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivFARM.java index 9d8e064b..72b76444 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivFARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivFARM.java @@ -11,7 +11,7 @@ public class DivFARM extends MachConcreteNode implements MachNode { @Override public RegMask outregmap() { return arm.DMASK; } // FDIV (scalar) - @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,0b000110); } + @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,arm.OPF_DIV); } // General form: "VDIF = dst /= src" @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" / ").p(code.reg(in(2))); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java index b2673396..45ecc430 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java @@ -22,7 +22,7 @@ public class FloatARM extends ConstantNode implements MachNode, RIPRelSize { short dst = (short)(enc.reg(this) - arm.D_OFFSET); double d = ((TypeFloat)_con).value(); long x = Double.doubleToRawLongBits(d); - enc.add4(arm.load_pc(0b01011100, 0, dst)); + enc.add4(arm.load_pc(arm.OPF_ARM, 0, dst)); } // Delta is from opcode start. @@ -31,7 +31,7 @@ public class FloatARM extends ConstantNode implements MachNode, RIPRelSize { // Delta is from opcode start @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { short dst = (short)(enc.reg(this) - arm.D_OFFSET); - enc.add4(arm.load_pc(0b01011100, delta, dst)); + enc.add4(arm.load_pc(arm.OPF_ARM, delta, dst)); } // Human-readable form appended to the SB. Things like the encoding, diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FunARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FunARM.java index eaea0ede..71e9ef87 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FunARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FunARM.java @@ -27,7 +27,7 @@ public class FunARM extends FunNode implements MachNode { _maxArgSlot = arm.maxSlot(enc._fun.sig()); _frameAdjust = (short) (_maxSlot+1 - _maxArgSlot); if( _frameAdjust == 0 ) return; // Skip if no frame adjust - enc.add4(arm.imm_inst(0b1001000100, (_frameAdjust*8)&0xFFF, arm.RSP, arm.RSP)); + enc.add4(arm.imm_inst(arm.OPI_ADD, (_frameAdjust*8)&0xFFF, arm.RSP, arm.RSP)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/I2F8ARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/I2F8ARM.java index f10e636a..5ecc98b6 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/I2F8ARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/I2F8ARM.java @@ -13,7 +13,7 @@ public class I2F8ARM extends MachConcreteNode implements MachNode { // SCVTF short self = (short)(enc.reg(this )-arm.D_OFFSET); short reg1 = enc.reg(in(1)); - int body = arm.float_cast(0b10011110, 1, reg1, self); + int body = arm.float_cast(arm.OP_FLOAT_C, 1, reg1, self); enc.add4(body); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/IntARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/IntARM.java index 9f9c6db6..8affb4c6 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/IntARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/IntARM.java @@ -33,11 +33,11 @@ public class IntARM extends ConstantNode implements MachNode { if(nb0 >= nb1) { // More 0 blocks then F blocks, use movz pattern = 0; - op = 0b110100101; + op = arm.OP_MOVZ; } else { // More F blocks then 0 blocks, use movn pattern = 0xFFFF; - op = 0b100100101; + op = arm.OP_MOVN; } int invert = pattern; for (int i=0; i<4; i++) { @@ -45,11 +45,11 @@ public class IntARM extends ConstantNode implements MachNode { x >>= 16; if (block != pattern) { enc.add4(arm.mov(op, i, block ^ invert, self)); - op = 0b111100101; + op = arm.OP_MOVK; invert = 0; } } - if (op != 0b111100101) { + if (op != arm.OP_MOVK) { // All blocks are the same, special case enc.add4(arm.mov(op, 0, 0, self)); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java index 1c3e2e49..7a7f06b8 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java @@ -21,9 +21,9 @@ public class LoadARM extends MemOpARM{ // ldr(immediate - unsigned offset) | ldr(register) @Override public void encoding( Encoding enc ) { if(_declaredType == TypeFloat.F32 || _declaredType == TypeFloat.F64) { - ldst_encode(enc, 0b1111110101, 0b11111100011, this, true); + ldst_encode(enc, arm.OPF_LOAD_IMM, arm.OPF_LOAD_R, this, true); } else { - ldst_encode(enc, 0b1111100101, 0b11111000011, this, false); + ldst_encode(enc, arm.OP_LOAD_IMM, arm.OP_LOAD_R, this, false); } } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslARM.java index 24790f9d..5c664c40 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslARM.java @@ -11,7 +11,7 @@ public class LslARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } - @Override public void encoding( Encoding enc ) { arm.shift_reg(enc,this,0b1000); } + @Override public void encoding( Encoding enc ) { arm.shift_reg(enc,this,arm.OP_LSL); } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" << ").p(code.reg(in(2))); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslIARM.java index 3a7fc76c..5e35b4c0 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslIARM.java @@ -24,7 +24,7 @@ public class LslIARM extends MachConcreteNode implements MachNode { assert _imm > 0; // UBFM <Xd>, <Xn>, #(-<shift> MOD 64), #(63-<shift>) // immr must be (-<shift> MOD 64) = 64 - shift - enc.add4(arm.imm_shift(0b1101001101, 64 - _imm, (64 - _imm) - 1, rn, rd)); + enc.add4(arm.imm_shift(arm.OPI_LSL, 64 - _imm, (64 - _imm) - 1, rn, rd)); } // General form: "lsli rd = rs1 << imm" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrARM.java index cdc0f301..f22c1264 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrARM.java @@ -11,7 +11,7 @@ public class LsrARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } - @Override public void encoding( Encoding enc ) { arm.shift_reg(enc,this,0b1001); } + @Override public void encoding( Encoding enc ) { arm.shift_reg(enc,this,arm.OP_LSR); } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" >>> ").p(code.reg(in(2))); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrIARM.java index 7b9241d0..e349d46f 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrIARM.java @@ -20,7 +20,7 @@ public class LsrIARM extends MachConcreteNode implements MachNode { short rd = enc.reg(this); short rn = enc.reg(in(1)); assert _imm > 0; - enc.add4(arm.imm_shift(0b1101001101,_imm, 0b111111, rn,rd)); + enc.add4(arm.imm_shift(arm.OPI_LSR,_imm, 0b111111, rn,rd)); } // General form: "lsri rd = rs1 >>> imm" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulARM.java index 5decb4de..261327cb 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulARM.java @@ -11,7 +11,7 @@ public class MulARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } - @Override public void encoding( Encoding enc ) { arm.madd(enc,this,0b10011011000,31); } + @Override public void encoding( Encoding enc ) { arm.madd(enc,this,arm.OP_MUL,31); } // General form: "rd = rs1 * rs2" @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" * ").p(code.reg(in(2))); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulFARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulFARM.java index a4862db5..89dba172 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulFARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulFARM.java @@ -9,7 +9,7 @@ public class MulFARM extends MachConcreteNode implements MachNode{ @Override public String op() { return "mulf"; } @Override public RegMask regmap(int i) { return arm.DMASK; } @Override public RegMask outregmap() { return arm.DMASK; } - @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,0b10); } + @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,arm.OPF_MUL); } // Default on double precision for now(64 bits) // General form: "VMUL.f32 rd = src1 * src2 @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NewARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NewARM.java index fff5dac2..face3cdd 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NewARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NewARM.java @@ -15,7 +15,7 @@ public class NewARM extends NewNode implements MachNode { @Override public void encoding( Encoding enc ) { // bl - enc.external(this,"calloc").add4(arm.b(0b100101, 0)); + enc.external(this,"calloc").add4(arm.b(arm.OP_CALL, 0)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java index c492d334..7efae38d 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java @@ -18,9 +18,9 @@ public class NotARM extends MachConcreteNode implements MachNode{ // subtracting zero from rs will just yield rs, it sets the zero flag and then it's used in cset short self = enc.reg(this ); short reg1 = enc.reg(in(1)); - int subs = arm.imm_inst(0b1111000100, 0, reg1, self); + int subs = arm.imm_inst(arm.OP_SUBS, 0, reg1, self); enc.add4(subs); - int cset = arm.cond_set(0b10011010100, 31, arm.COND.EQ, 63, reg1); + int cset = arm.cond_set(arm.OP_CSET, 31, arm.COND.EQ, 63, reg1); enc.add4(cset); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrARM.java index 860546d2..593c0c6c 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrARM.java @@ -11,7 +11,7 @@ public class OrARM extends MachConcreteNode implements MachNode { @Override public String glabel() { return "|"; } @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } - @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,0b10101010); } + @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,arm.OP_OR); } // General form: #rd = rs1 & rs2 @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" | ").p(code.reg(in(2))); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java index afd44306..fe58a299 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java @@ -15,7 +15,7 @@ public class OrIARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } @Override public void encoding( Encoding enc ) { - arm.imm_inst_n(enc, this, 0b101100100, _imm); + arm.imm_inst_n(enc, this, arm.OPI_OR, _imm); } // General form: "ori rd = rs1 | imm" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/RetARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/RetARM.java index b51b4879..ec32c1bc 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/RetARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/RetARM.java @@ -21,8 +21,8 @@ public class RetARM extends ReturnNode implements MachNode { @Override public void encoding( Encoding enc ) { int frameAdjust = ((FunARM)fun())._frameAdjust; if( frameAdjust > 0 ) - enc.add4(arm.imm_inst(0b1001000100, (frameAdjust*-8)&0xFFF, arm.RSP, arm.RSP)); - enc.add4(arm.ret(0b1101011001011111000000)); + enc.add4(arm.imm_inst(arm.OPI_ADD, (frameAdjust*-8)&0xFFF, arm.RSP, arm.RSP)); + enc.add4(arm.ret(arm.OP_RET)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java index 5c187239..03a78c5e 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java @@ -21,7 +21,7 @@ public class SetARM extends MachConcreteNode implements MachNode { // Encoding is appended into the byte array; size is returned @Override public void encoding( Encoding enc ) { - int body = arm.cset(0b1001101010011111, arm.make_condition(_bop), 0b0111111, enc.reg(this)); + int body = arm.cset(arm.OP_CSET,0b11111, arm.make_condition(_bop), 0b0111111, enc.reg(this)); enc.add4(body); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SplitARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SplitARM.java index b52533e0..a92f7f59 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SplitARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SplitARM.java @@ -24,31 +24,31 @@ public class SplitARM extends SplitNode { throw Utils.TODO(); } int off = enc._fun.computeStackSlot(dst - arm.MAX_REG)*8; - enc.add4(arm.load_str_imm(0b1111100100, off, src, dst)); + enc.add4(arm.load_str_imm(arm.OP_STORE_IMM, off, src, dst)); } if(src >= arm.MAX_REG) { // Load from SP int off = enc._fun.computeStackSlot(src - arm.MAX_REG) * 8; - enc.add4(arm.load_str_imm(0b1111100101, off, src, dst)); + enc.add4(arm.load_str_imm(arm.OP_LOAD_IMM, off, src, dst)); } // pick opcode based on regs if(!dstX && !srcX) { // GPR->GPR - enc.add4(arm.mov_reg(0b10101010000, src, dst)); + enc.add4(arm.mov_reg(arm.OP_MOV, src, dst)); } else if(dstX && srcX) { // FPR->FPR // fmov reg - enc.add4(arm.f_mov_reg(0b00011110, src,dst)); + enc.add4(arm.f_mov_reg(arm.OP_FMOV_REG, src,dst)); } else if(dstX && !srcX) { // GPR->FPR // FMOV(general) 64 bits to DOUBLE-PRECISION - enc.add4(arm.f_mov_general(0b10011110, 0b01, 0, 0b111, src, dst)); + enc.add4(arm.f_mov_general(arm.OP_FMOV, 0b01, 0, 0b111, src, dst)); } else if(!dstX && srcX) { //FPF->GPR // FMOV(general) DOUBLE-PRECISION to 64 bits - enc.add4(arm.f_mov_general(0b10011110, 0b01, 0, 0b110, src, dst)); + enc.add4(arm.f_mov_general(arm.OP_FMOV, 0b01, 0, 0b110, src, dst)); } } } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/StoreARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/StoreARM.java index 97ee6bb2..ffeac3eb 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/StoreARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/StoreARM.java @@ -24,9 +24,9 @@ public class StoreARM extends MemOpARM { @Override public RegMask outregmap() { return null; } @Override public void encoding( Encoding enc ) { if(_declaredType == TypeFloat.F32 || _declaredType == TypeFloat.F64) { - ldst_encode(enc, 0b1111110100,0b11111100001, val(), true); + ldst_encode(enc, arm.OPF_STORE_IMM,arm.OPF_STORE_R, val(), true); } else { - ldst_encode(enc, 0b1111100100, 0b11111000001, val(), false); + ldst_encode(enc, arm.OP_STORE_IMM, arm.OP_STORE_R, val(), false); } } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubARM.java index 072bbf46..feb59853 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubARM.java @@ -10,7 +10,7 @@ public class SubARM extends MachConcreteNode implements MachNode { @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } - @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,0b11001011); } + @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,arm.OP_SUB); } // General form: "sub # rd = rs1 - rs2" @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubFARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubFARM.java index 903c7947..0d8d3c10 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubFARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubFARM.java @@ -9,7 +9,7 @@ public class SubFARM extends MachConcreteNode implements MachNode { @Override public String op() { return "subf"; } @Override public RegMask regmap(int i) { return arm.DMASK; } @Override public RegMask outregmap() { return arm.DMASK; } - @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,0b1110); } + @Override public void encoding( Encoding enc ) { arm.f_scalar(enc,this,arm.OPF_SUB); } // Default on double precision for now(64 bits) // General form: "vsub.f32 rd = src1 + src2 @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java index 8aae5911..16b56553 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java @@ -18,10 +18,10 @@ public class TFPARM extends ConstantNode implements MachNode, RIPRelSize { enc.relo(this); short self = enc.reg(this); // adrp x0, 0 - int adrp = arm.adrp(1,0, 0b10000, 0,self); + int adrp = arm.adrp(1,0, arm.OP_ADRP, 0,self); // add x0, x0, 0 enc.add4(adrp); - arm.imm_inst(enc,0b1001000100,0, 0); + arm.imm_inst(enc,arm.OPI_ADD,0, 0); } @Override public byte encSize(int delta) { @@ -39,7 +39,7 @@ public class TFPARM extends ConstantNode implements MachNode, RIPRelSize { // patch upper 20 bits via adrp enc.patch4(opStart, arm.adrp(1, adrp_delta & 0b11, 0b10000, adrp_delta >> 2, rpc)); // low 12 bits via add - enc.patch4(next, arm.imm_inst_l(0b1001000100, delta & 0xfff, rpc)); + enc.patch4(next, arm.imm_inst_l(arm.OPI_ADD, delta & 0xfff, rpc)); } else { // should not happen as one instruction is 4 byte, and TFP arm encodes 2. throw Utils.TODO(); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/UJmpARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/UJmpARM.java index c2345a2e..4b2d14df 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/UJmpARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/UJmpARM.java @@ -20,7 +20,7 @@ public class UJmpARM extends CFGNode implements MachNode, RIPRelSize { @Override public Node idealize() { throw Utils.TODO(); } @Override public void encoding( Encoding enc ) { enc.jump(this,uctrl()); - int body = arm.b(0b01010100, 0); + int body = arm.b(arm.OP_UJMP, 0); enc.add4(body); } @@ -34,7 +34,7 @@ public class UJmpARM extends CFGNode implements MachNode, RIPRelSize { // Delta is from opcode start @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { if( opLen==4 ) { - enc.patch4(opStart,arm.b(0b01010100, delta)); + enc.patch4(opStart,arm.b(arm.OP_UJMP, delta)); } else { throw Utils.TODO(); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorARM.java index 9fdf0619..9afd2e5d 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorARM.java @@ -10,7 +10,7 @@ public class XorARM extends MachConcreteNode implements MachNode{ @Override public String glabel() { return "^"; } @Override public RegMask regmap(int i) { return arm.RMASK; } @Override public RegMask outregmap() { return arm.RMASK; } - @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,0b11001010); } + @Override public void encoding( Encoding enc ) { arm.r_reg(enc,this,arm.OP_XOR); } // General form: "rd = x1 ^ x2" @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" ^ ").p(code.reg(in(2))); diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorIARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorIARM.java index 429cdb38..be28fb28 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorIARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorIARM.java @@ -20,7 +20,7 @@ public class XorIARM extends MachConcreteNode implements MachNode { @Override public RegMask outregmap() { return arm.RMASK; } // General form: "xori rd = rs1 ^ imm" - @Override public void encoding( Encoding enc ) { arm.imm_inst_n(enc,this,0b110100100,_imm); } + @Override public void encoding( Encoding enc ) { arm.imm_inst_n(enc,this,arm.OPI_XOR,_imm); } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" ^ #").p(_imm); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java index ce78f85b..21d6aa98 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java @@ -90,6 +90,79 @@ public class arm extends Machine { static final RegMask D6_MASK = new RegMask(D6); static final RegMask D7_MASK = new RegMask(D7); + // major opcode: OP + public static int OP_ADD = 0b10_001_011; + public static int OPF_ADD = 0b00_011_110; + public static int OPI_ADD = 0b10_010_00100; + + public static int OP_UJMP = 0b01010100; + + public static int OP_ADRP = 0b10000; + + public static int OP_ASR = 0b1010; + public static int OPI_ASR = 0b10_0100_1101; + + public static int OP_LSL = 0b1000; + public static int OPI_LSL =0b1101001101; + + + public static int OP_LSR = 0b1001; + public static int OPI_LSR = 0b1101001101; + + public static int OP_BRANCH = 0b01_0101_00; + public static int OP_CALL = 0b10_010_1; + + public static int OP_CALLRARM = 0b1101011000111111000000; + + public static int OP_SUBS = 0b1111000100; + public static int OP_CSET = 0b10011010100; + public static int OP_CMP = 0b11101011; + public static int OPI_CMP = 0b1111000100; + + public static int OP_DIV = 0b10011010110; + public static int OPF_DIV = 0b000110; + + public static int OP_MUL = 0b10011011000; + public static int OPF_MUL = 0b10; + + public static int OPF_ARM = 0b01011100; + + public static int OP_FLOAT_C = 0b10011110; + + public static int OP_XOR = 0b11001010; + public static int OPI_XOR = 0b110100100; + + public static int OP_AND = 0b10_0010_10; + public static int OPI_AND = 0b10_0100_100; + + public static int OP_OR = 0b10101010; + public static int OPI_OR = 0b101100100; + + public static int OP_SUB = 0b11001011; + public static int OPF_SUB = 0b1110; + + public static int OP_MOVK = 0b111100101; + public static int OP_MOVN = 0b100100101; + public static int OP_MOVZ = 0b110100101; + + public static int OP_RET = 0b1101011001011111000000; + // Store/load opcodes + public static int OP_LOAD_R = 0b11111000011; + public static int OP_LOAD_IMM = 0b1111100101; + + public static int OPF_LOAD_R = 0b11111100011; + public static int OPF_LOAD_IMM = 0b1111110101; + + public static int OP_STORE_R = 0b11111000001; + public static int OP_STORE_IMM = 0b1111100100; + + public static int OPF_STORE_R = 0b11111100001; + public static int OPF_STORE_IMM = 0b1111110100; + + public static int OP_FMOV = 0b10011110; + public static int OP_FMOV_REG = 0b00011110; + // https://docsmirror.github.io/A64/2023-06/mov_orr_log_shift.html + public static int OP_MOV = 0b10101010000; // Calling convention; returns a machine-specific register // for incoming argument idx. // index 0 for control, 1 for memory, real args start at index 2 @@ -125,6 +198,10 @@ public class arm extends Machine { SXTX, } + static public int cset(int opcode, int rm, COND cond, int rn, int rd) { + return (opcode << 21) | (rm << 15) | (cond.ordinal() << 12) | (rn << 5) | rd; + } + static public int cset(int opcode, COND cond, int rn, int rd) { return (opcode << 16) | (cond.ordinal() << 12) | (rn << 5) | rd; } @@ -581,7 +658,7 @@ public class arm extends Machine { private Node sub(SubNode sub) { return sub.in(2) instanceof ConstantNode con && con._con instanceof TypeInteger ti && imm12(ti) - ? new SubIARM(sub, (int)ti.value()) + ? new AddIARM(sub, (int)(-ti.value())) : new SubARM(sub); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndRISC.java index 855821c8..ca2f4209 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndRISC.java @@ -9,7 +9,7 @@ public class AndRISC extends MachConcreteNode implements MachNode { @Override public String op() { return "and"; } @Override public RegMask regmap(int i) { return riscv.RMASK; } @Override public RegMask outregmap() { return riscv.WMASK; } - @Override public void encoding( Encoding enc ) { riscv.r_type(enc,this,7,0); } + @Override public void encoding( Encoding enc ) { riscv.r_type(enc,this,0b111,0); } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" & ").p(code.reg(in(2))); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java index 0adfe716..c2947bc1 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java @@ -18,7 +18,7 @@ public class CallRRISC extends CallNode implements MachNode { @Override public void encoding( Encoding enc ) { short rpc = enc.reg(this); short src = enc.reg(in(_inputs._len-1)); - int body = riscv.i_type(0x67, rpc, 0, src, 0); + int body = riscv.i_type(riscv.OP_CALL, rpc, 0, src, 0); enc.add4(body); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java index d5d56068..61efc658 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java @@ -19,9 +19,9 @@ public class FltRISC extends ConstantNode implements MachNode, RIPRelSize { enc.largeConstant(this,_con); short dst = (short)(enc.reg(this) - riscv.F_OFFSET); // AUIPC dst,#hi20_constant_pool - enc.add4(riscv.u_type(0b0010111, dst, 0)); + enc.add4(riscv.u_type(riscv.OP_AUIPC, dst, 0)); // Load dst,[dst+#low12_constant_pool] - enc.add4(riscv.i_type(0x07, dst, 0x03, dst, 0)); + enc.add4(riscv.i_type(riscv.LOAD_GPR, dst, 0b11, dst, 0)); } // Delta is from opcode start. @@ -32,9 +32,9 @@ public class FltRISC extends ConstantNode implements MachNode, RIPRelSize { @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { short dst = (short)(enc.reg(this) - riscv.F_OFFSET); // AUIPC dst,#hi20_constant_pool - enc.patch4(opStart , riscv.u_type(0b0010111, dst, delta)); + enc.patch4(opStart , riscv.u_type(riscv.OP_AUIPC, dst, delta)); // Load dst,[dst+#low12_constant_pool] - enc.patch4(opStart+4, riscv.i_type(0x07, dst, 0x03, dst, delta)); + enc.patch4(opStart+4, riscv.i_type(riscv.LOAD_GPR, dst, 0b11, dst, delta)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java index a6f84c19..2e0cb5d0 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java @@ -14,7 +14,7 @@ public class I2F8RISC extends MachConcreteNode implements MachNode { @Override public void encoding( Encoding enc ) { short dst = (short)(enc.reg(this )-riscv.F_OFFSET); short src1 = enc.reg(in(1)); - int body = riscv.r_type(0b1010011,dst,riscv.RM.RNE.ordinal(),src1,0,0x69); + int body = riscv.r_type(riscv.FLOAT_COMMON,dst,riscv.RM.RNE.ordinal(),src1,0,0x69); enc.add4(body); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java index 1a179556..239a2c5e 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java @@ -30,10 +30,18 @@ public abstract class MemOpRISC extends MemOpNode implements MachNode { // func3 is based on load/store size and extend int func3() { int func3 = -1; - if( _declaredType == TypeInteger. I8 ) func3=0; // LB SB - if( _declaredType == TypeInteger.I16 ) func3=1; // LH SH - if( _declaredType == TypeInteger.I32 ) func3=2; // LW SW - if( _declaredType == TypeInteger.BOT ) func3=3; // LD SD + // no unsigned flavour for store, so both signed and unsigned trigger the same + if(this instanceof StoreRISC) { + if( _declaredType == TypeInteger. I8 || _declaredType == TypeInteger.U8) func3=0; // SB + if( _declaredType == TypeInteger.I16 || _declaredType == TypeInteger.U16 ) func3=1; // SH + if( _declaredType == TypeInteger.I32 || _declaredType == TypeInteger.U32) func3=2; // SW + if( _declaredType == TypeInteger.BOT ) func3=3; // SD + return func3; + } + if( _declaredType == TypeInteger. I8 ) func3=0; // LB + if( _declaredType == TypeInteger.I16 ) func3=1; // LH + if( _declaredType == TypeInteger.I32 ) func3=2; // LW + if( _declaredType == TypeInteger.BOT ) func3=3; // LD if( _declaredType == TypeInteger. U8 ) func3=4; // LBU if( _declaredType == TypeInteger.BOOL) func3=4; // LBU if( _declaredType == TypeInteger.U16 ) func3=5; // LHU @@ -48,14 +56,21 @@ public abstract class MemOpRISC extends MemOpNode implements MachNode { // 7 bits, 00 000 11 or 00 001 11 for FP int opcode(Encoding enc) { - if( enc.reg(this) < riscv.F_OFFSET ) return 3; - else if( this instanceof StoreRISC ) - // opcode is the same for 32 bit and 64 bits - return 39; - return 7; + boolean isStore = this instanceof StoreRISC; + boolean isLoad = this instanceof LoadRISC; + short reg = enc.reg(isStore? val(): this); + assert reg != -1; + boolean isFloat = enc.reg(val()) >= riscv.F_OFFSET; + + if (isStore) return isFloat ? 39 : 35; + if (isLoad) return isFloat ? 7 : 3; + + return 0; } short xreg(Encoding enc) { - short xreg = enc.reg(this ); + boolean isStore = this instanceof StoreRISC; + short xreg = enc.reg(isStore? val() : this ); + assert xreg != -1; return xreg < riscv.F_OFFSET ? xreg : (short)(xreg-riscv.F_OFFSET); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java index 7dbdf9bb..8d84a012 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java @@ -22,8 +22,8 @@ public class NewRISC extends NewNode implements MachNode { enc.external(this,"calloc"); // A1 is a caller-save, allowed to crush building external address // auipc - enc.add4(riscv.u_type(0x17, riscv.A1, 0)); - enc.add4(riscv.i_type(0x67, riscv.RPC, 0, riscv.A1, 0)); + enc.add4(riscv.u_type(riscv.OP_AUIPC, riscv.A1, 0)); + enc.add4(riscv.i_type(riscv.OP_CALL, riscv.RPC, 0, riscv.A1, 0)); } // General form: "alloc #bytes PC" diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java index 41503da9..e04d3691 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java @@ -29,7 +29,7 @@ public class RetRISC extends ReturnNode implements MachNode { if( frameAdjust > 0 ) enc.add4(riscv.i_type(riscv.I_TYPE, riscv.SP, 0, riscv.SP, (frameAdjust*-8) & 0xFFF)); short rpc = enc.reg(rpc()); - enc.add4(riscv.i_type(0x67, riscv.ZERO, 0, rpc, 0)); + enc.add4(riscv.i_type(riscv.OP_CALL, riscv.ZERO, 0, rpc, 0)); } @Override public void asm(CodeGen code, SB sb) { diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java index 99345f51..875dd1ab 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java @@ -23,7 +23,7 @@ public class SetFRISC extends MachConcreteNode implements MachNode { short dst = enc.reg(this ); short src1 = (short)(enc.reg(in(1))-riscv.F_OFFSET); short src2 = (short)(enc.reg(in(2))-riscv.F_OFFSET); - int body = riscv.r_type(0x53,dst,riscv.fsetop(_bop),src1,src2,0); + int body = riscv.r_type(riscv.FLOAT_COMMON,dst,riscv.fsetop(_bop),src1,src2,0); enc.add4(body); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java index a322e8e4..4188c240 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java @@ -25,12 +25,14 @@ public class SplitRISC extends SplitNode { int off = enc._fun.computeStackSlot(dst - riscv.MAX_REG)*8; // store 64 bit values - enc.add4(riscv.s_type(39, 3, riscv.SP, dst, off)); + enc.add4(riscv.s_type(riscv.STORE_GPR, 0b11, riscv.SP, src, off)); + return; } if( src >= riscv.MAX_REG ) { // Load from SP int off = enc._fun.computeStackSlot(src - riscv.MAX_REG)*8; - enc.add4(riscv.i_type(7, dst, 3,riscv.SP, off)); + enc.add4(riscv.i_type(riscv.LOAD_GPR, dst, 0b11,riscv.SP, off)); + return; } // pick opcode based on regs if( !dstX && !srcX ) { @@ -39,16 +41,16 @@ public class SplitRISC extends SplitNode { } else if( dstX && srcX ) { // FPR->FPR // Can do: FPR->GPR->FPR - enc.add4(riscv.r_type(0b1010011, dst, 0, src, 0, 0b1110001)); - enc.add4(riscv.r_type(0b1010011, dst, 0, src, 0, 0b0100000)); - } else if( dstX && !srcX ) { + enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst, 0, src - riscv.F_OFFSET, 0, 0b1110001)); + enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst - riscv.F_OFFSET, 0, src, 0, 0b0100000)); + } else if(!srcX && dstX) { //GPR->FPR // fmv.d.x - enc.add4(riscv.r_type(0b1010011, dst, 0, src, 0, 0b0100000)); - } else if( !dstX && srcX ) { + enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst - riscv.F_OFFSET, 0, src, 0, 0b1111001)); + } else if(srcX && !dstX) { //FPR->GPR //fmv.x.d - enc.add4(riscv.r_type(0b1010011, dst, 0, src, 0, 0b1110001)); + enc.add4(riscv.r_type(riscv.FLOAT_COMMON, dst, 0, src - riscv.F_OFFSET, 0, 0b1110001)); } } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraRISC.java index e878df7f..3d20f02d 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraRISC.java @@ -10,7 +10,7 @@ public class SraRISC extends MachConcreteNode implements MachNode { @Override public String op() { return "sar"; } @Override public RegMask regmap(int i) { return riscv.RMASK; } @Override public RegMask outregmap() { return riscv.WMASK; } - @Override public void encoding( Encoding enc ) { riscv.r_type(enc,this,5,0x20); } + @Override public void encoding( Encoding enc ) { riscv.r_type(enc,this,0b101,0b00100000); } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" >> ").p(code.reg(in(2))); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java index b97117d5..1741340e 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java @@ -34,7 +34,7 @@ public class StoreRISC extends MemOpRISC { @Override public void encoding( Encoding enc ) { short val = xreg(enc); short ptr = enc.reg(ptr()); - int body = riscv.s_type(opcode(enc), func3()&3, ptr, val, _off); + int body = riscv.s_type(opcode(enc), func3()&7, ptr, val, _off); enc.add4(body); } diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java index 1eef56e9..d971bf33 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java @@ -19,9 +19,9 @@ public class TFPRISC extends ConstantNode implements MachNode, RIPRelSize { short dst = enc.reg(this); TypeFunPtr tfp = (TypeFunPtr)_con; // auipc t0,0 - int auipc = riscv.u_type(0b0010111, dst, 0); + int auipc = riscv.u_type(riscv.OP_AUIPC, dst, 0); // addi t1,t0 + #0 - int addi = riscv.i_type(0b0010011, dst, 0, dst, 0); + int addi = riscv.i_type(riscv.I_TYPE, dst, 0, dst, 0); enc.add4(auipc); enc.add4(addi); } @@ -38,9 +38,9 @@ public class TFPRISC extends ConstantNode implements MachNode, RIPRelSize { // AUIPC (upper 20 bits) // opstart of add int next = opStart + opLen; - enc.patch4(opStart,riscv.u_type(0b0010111, rpc, delta)); + enc.patch4(opStart,riscv.u_type(riscv.OP_AUIPC, rpc, delta)); // addi(low 12 bits) - enc.patch4(next,riscv.i_type(0b0010011, rpc, 0, rpc, delta & 0xFFF)); + enc.patch4(next,riscv.i_type(riscv.I_TYPE, rpc, 0, rpc, delta & 0xFFF)); // addi } else { // should not happen as one instruction is 4 byte, and TFP arm encodes 2. diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java index 1695d8fe..16d5da3a 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java @@ -101,7 +101,7 @@ public class riscv extends Machine { FA6_MASK, FA7_MASK }; - // + // major opcode: OP public static int OP_CUSTOM0 = 0b00_010_11; public static int OP_AUIPC = 0b00_101_11; @@ -116,6 +116,16 @@ public class riscv extends Machine { public static int OP_BRANCH = 0b11_000_11; public static int OP_RESERVED= 0b11_010_11; + public static int OP_CALL = 0b11_001_11; + + // major opcode: Store-Load + public static int LOAD_FLOAT = 0b00_001_11; + public static int LOAD_GPR = 0b00_000_11; + public static int STORE_FLOAT = 0b01_001_11; + public static int STORE_GPR = 0b01_000_11; + + public static int FLOAT_COMMON = 0b10_100_11; + //I_type opcode: 0010 0011 public static int I_TYPE = 0x13; @@ -134,6 +144,7 @@ public class riscv extends Machine { int body = r_type(OP,dst,func3,src1,src2,func7); enc.add4(body); } + public static void rf_type(Encoding enc, Node n, RM func3, int func7) { short dst = (short)(enc.reg(n )-F_OFFSET); short src1 = (short)(enc.reg(n.in(1))-F_OFFSET); |