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Diffstat (limited to 'chapter21')
| -rw-r--r-- | chapter21/README.md | 47 | ||||
| -rw-r--r-- | chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java | 5 | ||||
| -rw-r--r-- | chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java | 1 |
3 files changed, 45 insertions, 8 deletions
diff --git a/chapter21/README.md b/chapter21/README.md index f2c74e07..a4efb00d 100644 --- a/chapter21/README.md +++ b/chapter21/README.md @@ -1,16 +1,51 @@ # Chapter 21: Instruction Encoding and ELF -This chapter has encodings for: -*x86_64 v2*, -*RISC V 64I* -*Arm V8* +# Table of Contents +1. [Instruction Encodings](#instruction-encodings) +2. [AMD64](#amd64) +3. [ARM](#arm) +4. [RISCV](#riscv) +This chapter will add instruction encodings. +Instruction encoding refers to the representation of +machine instructions in a specific binary format defined by the +processor's instruction set architecture (ISA) + +After we established instruction selection, we need to encode the instructions before we can write them +into an ELF object file. + +Currently, we support these architectures: +### AMD64: +For *x86-64(amd64):*, we use the latest Intel manual for the [encoding rules](https://www.felixcloutier.com/x86/). + +### RISC-V: + +For *riscv* we currently target [RVA23U64](https://msyksphinz-self.github.io/riscv-isadoc/html/). +- ARM +Each of which has its own instruction encoding format. + +To avoid ambiguity, we define the sources of the information we use to encode the instructions: + +### ARMV8/AArch64 : +For *arm*(aarch64) we use this collection for the [encoding rules](https://docsmirror.github.io/A64/2023-06/index.html). +*Note*: We only support 64 bits ARM encodings. + +--- ## Instruction Encodings -## x86_64_v2 -*Source*: [^1] + +## AMD64 + +#### REX PREFIX +#### MODR/M +#### SIB +#### Displacement +#### Immediate +#### Indirect + +======= ## ARM diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java index 517d0831..2b089331 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java @@ -21,12 +21,13 @@ public class FloatARM extends ConstantNode implements MachNode { @Override public FloatARM copy() { return new FloatARM(this); } @Override public void encoding( Encoding enc ) { + enc.largeConstant(this,_con); short dst = (short)(enc.reg(this) - arm.D_OFFSET); double d = ((TypeFloat)_con).value(); long x = Double.doubleToRawLongBits(d); // Any number that can be expressed as +/-n * 2-r,where n and r are integers, 16 <= n <= 31, 0 <= r <= 7. - //arm.f_mov(30,3,imm8,self); - throw Utils.TODO(); + int body = arm.load_pc(0b01011100, 0, dst); + enc.add4(body); } // Human-readable form appended to the SB. Things like the encoding, diff --git a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java index 04569476..2ebcd781 100644 --- a/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java +++ b/chapter21/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java @@ -277,6 +277,7 @@ public class arm extends Machine { enc.add4(body); } + // share same encoding with LDR (literal, SIMD&FP) flavour public static int load_pc(int opcode, int offset, int rt) { return (opcode << 24) | (offset << 5) | rt; } |
