diff options
Diffstat (limited to 'chapter22/src/main/java/com')
6 files changed, 13 insertions, 8 deletions
diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java index 5fa68e19..6fd4274a 100644 --- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java +++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java @@ -17,7 +17,7 @@ public class LoadARM extends MemOpARM { super(ld, base, idx, off, 0); } @Override public String op() { return "ld"+_sz; } - @Override public RegMask outregmap() { return size() >= 4 ? arm.MEM_MASK : arm.RMASK; } + @Override public RegMask outregmap() { return size() >= 4 ? arm.MEM_MASK : arm.WMASK; } private static final int[] OP_LOADS = new int[]{ Arm64.OP_LOAD_IMM_8, Arm64.OP_LOAD_IMM_16, Arm64.OP_LOAD_IMM_32, Arm64.OP_LOAD_IMM_64, }; diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java index 5c388bab..ec017032 100644 --- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java +++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/NotARM.java @@ -19,9 +19,9 @@ public class NotARM extends MachConcreteNode implements MachNode{ // subtracting zero from rs will just yield rs, it sets the zero flag and then it's used in cset short self = enc.reg(this ); short reg1 = enc.reg(in(1)); - int subs = Arm64.imm_inst(Arm64.OP_SUBS, 0, reg1, self); + int subs = Arm64.imm_inst(Arm64.OP_SUBS, 0, reg1, 31); enc.add4(subs); - int cset = Arm64.cond_set(Arm64.OP_CSET, 31, Arm64.COND.EQ, 63, reg1); + int cset = Arm64.cset(Arm64.OP_CSET, 31, Arm64.COND.EQ, 31, self); enc.add4(cset); } diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java index da5e6d4b..ddd9797b 100644 --- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java +++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java @@ -215,7 +215,7 @@ public class arm extends Machine { public static void f_cmp(Encoding enc, Node n) { short reg1 = (short)(enc.reg(n.in(1))-D_OFFSET); short reg2 = (short)(enc.reg(n.in(2))-D_OFFSET); - int body = Arm64.f_cmp(0b00011110, 3, reg1, reg2); + int body = Arm64.f_cmp(0b00011110, 3, reg2, reg1); enc.add4(body); } @@ -327,7 +327,7 @@ public class arm extends Machine { private Node cmp(BoolNode bool){ Node cmp = _cmp(bool); - return new SetARM(cmp, IfNode.negate(bool.op())); + return new SetARM(cmp, bool.op()); } private Node _cmp(BoolNode bool) { if( bool.isFloat() ) diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java index 469221f3..6aefc54b 100644 --- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java +++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NotRISC.java @@ -15,7 +15,8 @@ public class NotRISC extends MachConcreteNode implements MachNode { @Override public void encoding( Encoding enc ) { short dst = enc.reg(this ); short src = enc.reg(in(1)); - enc.add4(RiscV.i_type(RiscV.OP_IMM, dst, 2, src, 1)); + // SEQZ is unsigned: negative nonzero inputs must also produce false. + enc.add4(RiscV.i_type(RiscV.OP_IMM, dst, 3, src, 1)); } @Override public void asm(CodeGen code, SB sb) { sb.p(code.reg(this)); } } diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java index f270bf12..8b6512e1 100644 --- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java +++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java @@ -7,7 +7,11 @@ import com.seaofnodes.simple.node.Node; public class SetIRISC extends ImmRISC { final boolean _unsigned; // slti vs sltiu public SetIRISC( Node src, int imm12, boolean unsigned ) { - super(src,imm12); + this(src,imm12,unsigned,true); + } + public SetIRISC( Node src, int imm12, boolean unsigned, boolean pop ) { + super(src,imm12,pop); + if( !pop ) _inputs.setLen(2); _unsigned = unsigned; } @Override public String op() { return "slt" + (_unsigned ? "u":"") + "i"; } diff --git a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java index a1e3b767..f2d1e0b9 100644 --- a/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java +++ b/chapter22/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java @@ -305,7 +305,7 @@ public class riscv extends Machine { // x <= y - flip and negate; !(y < x); `slt tmp=y,x; xori dst=tmp,#1` case "<=" -> new XorIRISC(new SetRISC(bool.swap12(), false),1,false); // x == y - sub and vs0 == `sub tmp=x-y; sltu dst=tmp,#1` - case "==" -> new SetIRISC(new SubRISC(bool),1,true); + case "==" -> new SetIRISC(new SubRISC(bool),1,true,false); default -> throw Utils.TODO(); }; } |