| Commit message (Collapse) | Author | Age | Files | Lines |
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A bunch of minor README fixes, missing TOC, grammer cleanup
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Renumber chapters 10a, 10b, 11, 12, 13, 14 -> 10, 11, 13, 12, [11,14].
Split ch 17 into a 17a and 17b; shuffle around im/mutable syntax to be consistent, and present it more slowly.
THe new immutable syntax is pushed through all later chapters
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Same as the graph viewer, moves a lot of code out of all Nodes
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* Extend and backport SubNode peephole
* Add tests
* Restrict subtraction zero peepholes to integer operands
Require resolved integer mode in chapter 25 so zero subtraction preserves floating-point signed zero. Keep nonnumeric operands in the graph for subtraction diagnostics.
Add signed-zero coverage from chapter 12 and null-subtraction diagnostics from chapter 22. Confirmed the regressions fail on the original PR. Full Make suites pass in chapters 4-25 (5462 tests), including fresh chapter 25 sys.o compilation.
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
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all chapters, a little sharper for int ops
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Phis stay with regions, stop sinks to bottom,
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Unify dominator caching.
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The three comment lines above `AddNode.phiCon(this, ...)` in BoolNode were
copy-pasted from MulNode and never adapted: they use `*` as the operator and
describe the rotated shape `(x * (phi cons)) * con`.
For BoolNode neither is right. The operator is a compare, and in chapters
6-9 `rotate` is hard-coded `false`, so the rotated shape is never matched;
the shapes actually handled are `(phi cons) cmp con` and
`(phi cons) cmp (phi cons)`.
Reword the comment accordingly, and in chapters 6-9 add a line noting why
rotate is off. Chapters 10-25 pass `this instanceof EQ`, so no such claim is
made there.
Comment-only change; no code is touched.
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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* merge fixup
* More x86,risc,arm call convention fixes
Collect callee and caller save masks (inverts of each other, except for spills).
Reorg layout to be closer to each other; remove dead mask definitions; add final keyword
* lui fix up with 32 bit immediates
* Callee-save registers
Callee-save registers and masks and inserting LRGs for same and spilling and picking good spills. Insert CalleeSaveNodes and edges to RetXXXs and RegMasks for those edges.
Iterators for regmask.
Better printing post-allocation
* RegMask supports 128 bits
All regs available arm, risc.
MergeSort compiles & runs
* added flags splitting
* Fix risc5 compares
No flags on risc5.
Branch takes 2 inputs (one can be imm12).
Float compare only sets a GPR to 0/1.
Bool has a isFloat
Common risc5 imm-form handling
* extend test cases
* imm encoding, flags fixed
* grep for Todo: relocs
* float riscv fixed
* flags for set
* lui fix for small bits [0, 12]
* arm init
* arm last touches
* fmov still needs fix
* minor fixes
* minor fixes(2)
* got rid of unnecessary stuff
* create ch21
* remove encodings from chapter20 dir
* 1/2 pass cleaning up ARM encoding API
* ARM encoding compiles
* Risc R_TYPE and I_TYPE
* Progress RISC encodings
Missing lots of stuff still
* progress risc encoding
* risc encodings compile
* Update README.md
* Fold up redundant OP/OP-FP risc5 encoding
* x86 mem opcodes first cut
break out MemOp encodings into parts; change x86 indirectAdr to use Encoding class, remove redundant asserts & code
* x86 mem op encodings
* x86 reg+imm forms
* most reg-reg forms
* More x86 encodings
* Last few encodings
* switch to binary literals over decimals for opcodes
* logical immediates fixed, bitwise ops imm forms
* tfp and setArm fixed
* PC relative float for riscv
* readme init
* Merged pr/169
* Fixed the array1 test encodings
Clean up branch invert logic during BB layout
Cleanup branch target printing for RISC,ARM
ImmRISC ops mask imm12 to 12 bits
Fix NewRISC; hardcode RPC as part of call
Fix RISC inverting branchs >,>=
* floatarm encoding
* tfparm and intarm
* uncontional jump encoding for arm and riscv
* smarter IntARM, Intx86 does not always include rex.
* REX after PREFIX
* fixup load and store indirect
* updated rex prefix, if its 0x40 then its not needed
* Rex fix for floats, got rid of unnecessary stuff.
* rename to camel case, better param name
* add test export
* merged
* store opt
* store and load optimised forms handled
* tfp patch
* Store/load float arm/riscv/x64
* got rid of debug print
* splits for x86, riscv and arm
* readme fixups
* fix global symbol numbering for constants
* fix TFP pathc on arm and riscv, keep symbols in good order.
* fix opcode for store and loads, memOpRisc for Store and splitting
* replace hard coded opcodes with major opcodes
* replace hard coded opcodes with major opcodes
* add asserts and fix reg numbering
* add asserts and fix reg numbering
* minor updates
* revert changes
* remove constant pool from encoder TODO: add flag for JIT
* extend test cases
* minor fixes
* minor fixes
* update float test case
* stringHash fix on x64
* remove conditional ConstantPool write
* brainfuck minor fixes
* minor arm fixes
* split fix
* brainfuck and fib
* brain fuck
* arg_count, person
* add ignore
* typo
* riscv test sieve attempt
* minor changes
* riscv5 emulator additions
* arm eval setup
* Update riscv.java
* arm eval basics
* delta fixes
* arm fixes
* testfib arm
* arg_count
* small update for test newton
* small update for test newton
* testNewton runs on x64, riscv and arm
* arm additions
* arm pc eval fix
* arm workings
* debugging
* Progress sieve on ARM
Most ops need WMASK as the output, to exclude RSP.
calloc sentinal changes to multiple of 4
NewArm needs to set arg X0 to #1; arg X1 is length.
Fix EvalARM calling calloc & not advancing PC.
Fix EvalARM using ints vs longs.
Fix EvalARM missing AndI encoding.
* Fix some arm encoding
Fix some OBOB in R5 calloc encoding.
Sort EvalArm by major opcodes.
Add ASL. Remove leading switch. Fix OBOB in calloc.
Fix shift in ld/st with reg+offset
* arm sieve test
* test person push
* brainFuck arm
* "and" "or" syntactic sugar
* update encoding
* ch23 `and` `or`
* hack parse trinary for and, or
* close
* fixed or issue
* Update CallEndNode.java
* fix type issue
* fixed
* Adjust parseTrinary precedence vs && ||
* Fix arm simulation return
* Formatting
* Formatting
* simplify rn to be always 0.
* ch24 init
* stacked rel
* stack init
* stack rel
* remove parenthesis
* got rid of old test case
* update
* upgrade eval
* arm encoding bugs
encodeing cset had a shift wrong
eval missed using 0 for r31
* remove debug prints
* force main to encode first
* fix for missing main
* got rid of debug prints
* backwards with ch23
* simple new test cases
* update test cases
* enable old test
* got rid of own test case
* fix test11
* inline Api
* inline x86_64
* inline test cases
* fix stacked_r_5
* got rid of redundant rdid -1 set
* Several new fuzzer addDeps/keep bugs.
Fix risc/arm spill code values for passing 20 args.
* Update README
Move ch23_ch24 branch into ROADMAP
* Create TypeAnalysis.md
* Update TypeAnalysis.md
* Update TypeAnalysis.md
* More lattices for main
* Update TypeAnalysis.md
* Update TypeAnalysis.md
* TypeAnalysis continued
* fix typos
* pointers
* typo fix in reader
* Update TypeAnalysis.md
* sccp first attempt
* test
* init
* still debug
* Update TypeAnalysis.md
* more examples
* More docs
* Update TypeAnalysis.md
* widen phi nodes in loops
* extra debug stuff for opto
* Work in progress opto pass
* Progress on opto
* opto missing deps
ConFldOff needs String.equals in `eq`
Fix monotonic xfer functions in
- CallENd, CProj, Load, Arith
Mostly if either TOP or BOT inputs, the output is the matching TOP or BOT
* push mid-progress
* progress sccp
* Make all the default parser integer types pre-widen
Function sigs to calls allow wide ints
* progress sccp
* Update TypeInteger.java
* progress SCCP
* Progress SCCP
* Progress SCCP
A series of minor fixes, generally making transfer functions monotonic, or p[reserving sanity for error test cases.
* Progress on opto
Most tests pass, a few failures remain.
Split Opto code into a seperate file.
Improve `compute` precision in several places showing up during opto.
bugfix: "split-thru-phis" on Parms changes calling conventions. Not ready for that yet.
* most tests pass
Handle non-default main.
Simplify trivial inlining cutout test.
ParmNode excludes most Phi opts
Region idom excludes dead paths
RPC now interns
* Fix arm NOT encoding
* all tests pass
Float math handles high types monotonically
Minus node does not reset int widen.
Phi widen handles non-int mintype
Dead returns do not error complain.
Better handling default vs dead main
* If NewNode is high, produce high results
* BrainFuck uses a string
* README
* Update README.md
* Typos from copilot review
* monotonic fix MinusF
* Update TypeAnalysis.md
* Update TypeInteger.java
---------
Co-authored-by: Hadházy Tamás <helsgithub15@gmail.com>
Co-authored-by: Tamás Hadházy <85063808+Hels15@users.noreply.github.com>
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* READMEs
* Update README.md
* Update README.md
* Move printing into print dir
* Move codegen into codegen
* Framework for Reg Alloc
* First cut BuildLRG
RegMask.EMPTY -> null
* Setup for first simple split
* First cut split code for mismatch regs
* Live Ranges U-F
BuildLRG for Phi
Add CmpFX86
* FPR return
CallEndX86 needed to tell fp return from gpr ret
Call has no output regs.
* Next cut regalloc
Building IFG.
Coloring.
Some nested spilling
Optimize divf/con -> mul times inverse
* RISC-V basic isel (#156)
* Initial push
Major CodeGen cleanup; most static globals move into the CodeGen object.
* Minor progress bug with mutual recursion
* Add test from pr#148
* First cut x86 "port"
Only "return 0;", no registers, no encoding, but yah gotta start somewhere
* Update README.md
* Update README.md
* Update ListScheduler.java
* command line launcher for simple
Parser bug fref in args
Some new test cases.
* Add basic RegMask for more than 64 bits of register mask.
Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension
* ASM Printer
InstSel handles folding 2+ ideal ops into 1 machine op
* handle instSel for some control flow
Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.
* Basic if-block inst selects and asm prints
* Add mul-by-coinstant to shift
* left shift codegen basic
* exclude RSP from *write* mask
* 2-arg add (not immediate)
mul-by-small constant opt. Some utilities.
* Handle first loop
Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates
* inst select for new struct allocation
* Float, bitwise and arithmetic operands codegen x86-64 (#150)
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* Remove non-exsting FP+imm ops
* Handle first loop
Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates
* float ops without imm values
* merge
* merge
* inst select for new struct allocation
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* Remove non-exsting FP+imm ops
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* float ops without imm values
* merge
* merge
* Rebased on ch 19
* Update tests
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* cleanup after merge
alpha-sort helper fcns
implicit test vs zero/null
* Add LEA op
asm print works on ideal nodes for all tests
* Minor cleanup lea
* merge2
* merge3
* GCM for float ops fixed, other cleanup - small extensions
* x86 addressing modes during inst select
Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate
* call setup
* extended ch13, 14,15,16 (#153)
* merge2
* merge3
* Fix a few minor fuzzer bugs
* Force array layout
ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.
* Fix a bunch of float issues
was deleting required inputs
* simpler invariant
defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).
* Call & CallR X86 instructions
* merge2
* Add-from-memory op
Remove FP immediate forms.
* Remove name from TFP
Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.
* remove debug prints
add check for bad call convention
fix 3 tests (bad merge?)
* cleanup call convention abi
Needs more love at some point...
* one more cleanup ABI
* New (#154)
* merge2
* merge3
* GCM for float ops fixed, other cleanup - small extensions
* call setup
* merge2
* remove debug prints
add check for bad call convention
fix 3 tests (bad merge?)
* cleanup call convention abi
Needs more love at some point...
* one more cleanup ABI
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* Add CmpMem form
Common addressing mode print
LEA can skip a base
* Add a AddFMemX86
A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.
* Docs
* XMM reg mask fix
Minor README updates
* Allow inverted cmp/mem
narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info
* Support "*ptr op= val"
at least for MemAdd
* missed golden rule update
* Array len is u32
load-after-store zero/sign-extends if the store is truncating
* One more missed case
* riscv init
* added not imm form bitwise shifts and ops plus test cases
* addressing modes(high chance it'll get deleted)
* fix minor bug
* delete non existing matches
* replace RegMask.Empty with null
* riscv handle store and load, fltRisch uses risc reg now
* load float into GPR and then later in RA do hard split.
* minor changes
* turn off ch20 tests
* Update Chapter20Test.java
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* Bring pr/154 to ch 20
RISC5 changes.
Some missing x86 ops.
Still needs some calling convention love.
* First cut regalloc working
Biased coloring; tracking splits around a LRG.
Separate split for self-conflicts.
postColor to remove junk splits.
Some minor riscv fixes.
* Compile some riscv codes
If SplitEmptyMask does not apply, fall back to normal split.
Missing CmpFRISC.
Renamed riscv flags.
RetRISC handls FPR
remove extra RegMask constructurs
* Progress reg alloc
Handle multi-node projections.
A little smarter about 2-addr scheduling
RegAlloc must-have single registers removes from other masks instead of interfering; had the mask removal backwards in a few cases.
LRG/RegMask COW expand masks before mutating.
Clone small constants instead of spilling.
Alloc & ProjX86 get output reg masks.
Full print large reg masks with sp+offset
* UF LRGs can be null during coloring
* Finish UF find
* README updates
* Fix ch19 mis-merge?
* x86 call args, risc5 load/store regs
* Push RISC WMASK
avoid writing to RSP
* Progress calling convention allocations
Call unlinks before reg alloc.
CallEnd tracks RPC
CallX86 requires TFP for correct ABI
Bias Color tracks 2-addr.
RPC gets a mask/stack-slot
Clean up call/fun ABI
Fix mask RET, RET_F
Fix print stack slot
Remove isMultiHead, isMultiTail
Better all-asm print
* Beef up Newton test
* Clean pass normal tests
New fcn print upgrades several golden rule tests.
Move the unlink-all from the walk::err call (which IS used during IterPeeps) to GCM.
CallEnd upgrades return type based on constant call.
Fix unlink to also unlink CallEnd
Constant TFP print checks constant
Tested an untested Load
* Arm basics, minor changes in riscv (#160)
* Initial push
Major CodeGen cleanup; most static globals move into the CodeGen object.
* Minor progress bug with mutual recursion
* Add test from pr#148
* First cut x86 "port"
Only "return 0;", no registers, no encoding, but yah gotta start somewhere
* Update README.md
* Update README.md
* Update ListScheduler.java
* command line launcher for simple
Parser bug fref in args
Some new test cases.
* Add basic RegMask for more than 64 bits of register mask.
Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension
* ASM Printer
InstSel handles folding 2+ ideal ops into 1 machine op
* handle instSel for some control flow
Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.
* Basic if-block inst selects and asm prints
* Add mul-by-coinstant to shift
* left shift codegen basic
* exclude RSP from *write* mask
* 2-arg add (not immediate)
mul-by-small constant opt. Some utilities.
* Handle first loop
Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates
* inst select for new struct allocation
* Float, bitwise and arithmetic operands codegen x86-64 (#150)
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* Remove non-exsting FP+imm ops
* Handle first loop
Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates
* float ops without imm values
* merge
* merge
* inst select for new struct allocation
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* Remove non-exsting FP+imm ops
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* float ops without imm values
* merge
* merge
* Rebased on ch 19
* Update tests
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* cleanup after merge
alpha-sort helper fcns
implicit test vs zero/null
* Add LEA op
asm print works on ideal nodes for all tests
* Minor cleanup lea
* merge2
* merge3
* GCM for float ops fixed, other cleanup - small extensions
* x86 addressing modes during inst select
Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate
* call setup
* extended ch13, 14,15,16 (#153)
* merge2
* merge3
* Fix a few minor fuzzer bugs
* Force array layout
ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.
* Fix a bunch of float issues
was deleting required inputs
* simpler invariant
defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).
* Call & CallR X86 instructions
* merge2
* Add-from-memory op
Remove FP immediate forms.
* Remove name from TFP
Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.
* remove debug prints
add check for bad call convention
fix 3 tests (bad merge?)
* cleanup call convention abi
Needs more love at some point...
* one more cleanup ABI
* New (#154)
* merge2
* merge3
* GCM for float ops fixed, other cleanup - small extensions
* call setup
* merge2
* remove debug prints
add check for bad call convention
fix 3 tests (bad merge?)
* cleanup call convention abi
Needs more love at some point...
* one more cleanup ABI
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* Add CmpMem form
Common addressing mode print
LEA can skip a base
* Add a AddFMemX86
A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.
* Docs
* XMM reg mask fix
Minor README updates
* Allow inverted cmp/mem
narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info
* Support "*ptr op= val"
at least for MemAdd
* missed golden rule update
* Array len is u32
load-after-store zero/sign-extends if the store is truncating
* One more missed case
* riscv init
* added not imm form bitwise shifts and ops plus test cases
* addressing modes(high chance it'll get deleted)
* fix minor bug
* delete non existing matches
* replace RegMask.Empty with null
* riscv handle store and load, fltRisch uses risc reg now
* load float into GPR and then later in RA do hard split.
* minor changes
* turn off ch20 tests
* Update Chapter20Test.java
* add riscv port to readme
* arm init
* work in progress
* arm2 bs
* work in progress
* clearnup arm
* fixed main pr problems
* regmask extra comments
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* Update Chapter20Test.java
* Weaken range-check test
since no range checks... test cannot fail (pass)
* Fix issue #161
Error adding 'null' and '5'
* bug fixs, cloning constants
Fix bug missing Find.
Fix bug setDef does unordered removal from basic blocks.
Use cloned constants for spilling.
* RA fixes
SplitSelfConflict MUST split before uses and after defs.
Split global constants across functions
Missing find in union;
Inserting split after new inserted wrong place
Pre-remove null LRGs before color.
Bias color hunts through Phis
Shorten InstructionSelection.
Rename !unified() to leader()
AddMemX86 is 2-addr
Add CastXXX to preserve register across cast.
* Allow a killMap to kill regs.
Bugfix scheduler.
Bugfix spiller - self-conflict order depended on hashtable iteration order, which depended on System.hashCode which would vary run to run.
Improvements to coloring
Improvements to spill quality testing
* Added flags-kill for XOR
* Missing add-deps from fuzzer
* Update Chapter14Test.java
* remove jukn files
* minimal "make release"
* Add regkills in IFG building
Fix bug LRG union stats
Adjust self-conflict splits to be slightly less aggressive
In every use-side split, dont split-after-split same block.
NewNode is a multi, does not define a register
* RA improvements
Attempt to commute to keep reg-masks compatible.
Clones with kills (x86 XOR killing flags to zero) fail before the flag-def.
Bugfix failed to color last lrg.
More smarts on picking trivial LRGs during coloring
Drop isSplit, add SplitNode
Pass regalloc round to all splits for debugging
Self-conflict no split on loop backedge.
Handle split that gets made goes dead
No-reg-mask spilling handles case with many def/uses.
Add DivIX86
BrainFuck, MergeSort now allocate as testing
* Push l,ast change, unbreak branch
* Finally pass the `new [u8]` double-copy test
* Fix several ARM reg setup problems
Finish Split bypass check
ARM: rsp is also a fixed zero, in R31. R0 is a valid register.
CallArm prints args, passes TFP for arg selection. Does not return a register. All CallEndARM which DOES return a register. Parms missing tfp for float args. ProjARM after a New missing regs. RetARM missing RPC.
Remove hopeful DivIX86
* Bunch of minor arm, risc fixes
small constants not cloning
* Much ARM fixage
One More Go-Round with Better Biased Colors
Fix bug picking deepest spills to bias.
ARM: remove default 2-address. Fix regmask overflow. Rename some ops to be canonical.
* Fixes to release
Port does not have to be in a Simple named directory.
Call convention is just a string, no enum
Missed some tests running RISC, ARM.
* Minor release change to allow another foreign port
* Allowing non-Simple repo ports
Expanding public API slightly so alternative (non-Simple repo) ports can happen.
RegMask supports single-bit-set and a long bitmask.
Bugfix GCM splitting multiple global constants.
Bugfix LCM grabbing a projection vs multi
Bugfix RegAlloc when avoiding splitting a clonable
Source code in release
More timing in CodeGen
* Cleanup call ABI presentation
Everybody uses the same names, same code shapes
* Caller save regs
...not callee save yet
* Expose caller save regs
* More x86,risc,arm call convention fixes
Collect callee and caller save masks (inverts of each other, except for spills).
Reorg layout to be closer to each other; remove dead mask definitions; add final keyword
* Callee-save registers
Callee-save registers and masks and inserting LRGs for same and spilling and picking good spills. Insert CalleeSaveNodes and edges to RetXXXs and RegMasks for those edges.
Iterators for regmask.
Better printing post-allocation
* RegMask supports 128 bits
All regs available arm, risc.
MergeSort compiles & runs
* Fix risc5 compares
No flags on risc5.
Branch takes 2 inputs (one can be imm12).
Float compare only sets a GPR to 0/1.
Bool has a isFloat
Common risc5 imm-form handling
* yank MulIRISC
* fix arg flags reg
Arm split op can spill flags
bugfix RegAlloc 1st real >=64bit reg num
* Update Chapter20Test.java
* Turn off transpile tests
which are broken for some time now
* A lot more readme
* better flags
ListScheduler stalls cmp/jmp in the same block; avoids some flags spills.
Make CmpIX86/ARM rematieralize.
Bugfix: remove some include x86/risc/arm in other dirs.
Canonicalize boilerplate fcn order
* regalloc improves
Use FltRISC, not clonable requires a spill from int->flt regs.
new splits track origin LRG, so later splits in the same pass know what lrg a spilled input is.
* RA improvements & fixes
Bugfix on split loop-depth computation.
Track killmask kills, which are always capacity kills and require more spilling.
Rename the riscv registers canonically, so I can tell them part! Definitely no GP or TP in Simple.
Node insertAfter bypass a little more conservative.
* RA bugfix
remove unified failed live ranges
* easier access for remote ports
debug support
* Lots more comments
* bugfix
infinite peep cycle on (17 ^ 3.14), i.e. bad program
* Fix imm12 shift
---------
Co-authored-by: Tamás Hadházy <85063808+Hels15@users.noreply.github.com>
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* remove unused method lazyFRef
* remove unused method copyF(Node, Node)
* make TypeMemPtr constants final
* make ConstantNode value final
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* Initial push
Major CodeGen cleanup; most static globals move into the CodeGen object.
* Minor progress bug with mutual recursion
* Add test from pr#148
* First cut x86 "port"
Only "return 0;", no registers, no encoding, but yah gotta start somewhere
* Update README.md
* Update README.md
* Update ListScheduler.java
* command line launcher for simple
Parser bug fref in args
Some new test cases.
* Add basic RegMask for more than 64 bits of register mask.
Add calling convention basics to X86; con+ret RegMasks.
GCM computes CFG for all users.
Drop unused MultiUse.
Pick up reg-pressure aware ListScheduler.
Re-layout CodeGen file to get code & data chunks nearer each other.
minor Ary extension
* ASM Printer
InstSel handles folding 2+ ideal ops into 1 machine op
* handle instSel for some control flow
Bool,If,CProj,Region,Phi
Handle 2-op expansions
Shuffle instSel graph walk back again.
* Basic if-block inst selects and asm prints
* Add mul-by-coinstant to shift
* left shift codegen basic
* exclude RSP from *write* mask
* 2-arg add (not immediate)
mul-by-small constant opt. Some utilities.
* Handle first loop
Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates
* inst select for new struct allocation
* Float, bitwise and arithmetic operands codegen x86-64 (#150)
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* Remove non-exsting FP+imm ops
* Handle first loop
Change inst sel walk again to pre-order, to set an early visit bit to stop cycles.
CFGNode copies dom/loop info.
Cmp not-immediate form.
Ret/Fun lazy updates
* float ops without imm values
* merge
* merge
* inst select for new struct allocation
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* Remove non-exsting FP+imm ops
* left shift codegen basic
* sar codegen basic
* merge
* some basic ops
* addf
* divf, subf, mulf
* rsp allowed in bitwise input, not output
* formatting
* float ops without imm values
* merge
* merge
* Rebased on ch 19
* Update tests
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* cleanup after merge
alpha-sort helper fcns
implicit test vs zero/null
* Add LEA op
asm print works on ideal nodes for all tests
* Minor cleanup lea
* x86 addressing modes during inst select
Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores.
Basic load/store for now, op-to-mem comes later
add same becomes Shl by 1.
Drop DivF-immiedate
* extended ch13, 14,15,16 (#153)
* merge2
* merge3
* Fix a few minor fuzzer bugs
* Force array layout
ld/st get size (but not signed/unsigned)
Add unsigned LT for later range checks.
* Fix a bunch of float issues
was deleting required inputs
* simpler invariant
defensive copy inputs for simpler invariant in complex sharing patterns
inc/dec form (just the opcode now).
* Call & CallR X86 instructions
* Add-from-memory op
Remove FP immediate forms.
* Remove name from TFP
Never shoulda been there (but was convenient for awhile).
Moved into FunNode, found by checking the linker table with a TFP.
* New (#154)
* merge2
* merge3
* GCM for float ops fixed, other cleanup - small extensions
* call setup
* merge2
* remove debug prints
add check for bad call convention
fix 3 tests (bad merge?)
* cleanup call convention abi
Needs more love at some point...
* one more cleanup ABI
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
* Add CmpMem form
Common addressing mode print
LEA can skip a base
* Add a AddFMemX86
A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.
* Docs
* XMM reg mask fix
Minor README updates
* Allow inverted cmp/mem
narrowing stores can bypass an AndMask
Array length loads do not need control
Some missing print info
* Support "*ptr op= val"
at least for MemAdd
* missed golden rule update
* Array len is u32
load-after-store zero/sign-extends if the store is truncating
* One more missed case
---------
Co-authored-by: hadha <helsgithub15@gmail.com>
Co-authored-by: Tamás Hadházy <85063808+Hels15@users.noreply.github.com>
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Parse as "arg - -2" and not "arg-- 2" which is a syntax error
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was making 10000 lines of ignored output
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Move x-x==0 to compute.
Add x/1 ==> x
All chapters
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Split Ch13 tests from Chapter12Test.java
Handle forward refs never defined.
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* Backport test exception handling to chapter 1
* Add unary ! to chapter 10 and 11 grammars
* Lex { } ! as punctuation
* Forward-port format whitespace
* Forward-port test organization
* Forward-port replace build-graphs.sh with Makefile
* Add chapter title to chapter 11
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* Fix unexpected number parse errors
* Add chapter titles
* Split test files by chapter
* Backport rename Fuzzer08Test to FuzzerWrap
* Replace graph build scripts with Makefile
* Backport Chapter05Test.testRegress1
* Backport require space after 'return'
* Backport check EOF after return statement
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* Trim trailing whitespace
* Ensure final new lines
* Convert line endings from CRLF to LF
* Replace tabs with spaces
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* chapter9
* merge fixes to chapter8
* Ch 9 notes
* Ch 9 work
Add a Iterate phase, after parsing.
Add a Worklist with fast dup removal & rand pull.
Add a Node.iter() call which returns progress or null. Peephole calls it. Iter() also asserts that Types make monotonic progress.
Intern all types, so we can do a cheap/easy "isa" test.
* GVN
* rename temporarily
* Apply Cliff's worklist changes
* Apply Cliff's GVN changes
* Revert "GVN"
This reverts commit 9dc6db1cac7e40de4a58333cbc3c9c3e7c088e6f.
* Revert "Ch 9 work"
This reverts commit df5b74e6c017a4f237a5d1a550a83b40a7928876.
* Fix 3-1+2
Was computing as 3-(1+2) == 0, not 4 as expected.
Add tests.
Unlock in swap12.
* Missed some cut-n-paste changes
* Break up the test file per-chapter
* Fix keep-alive while looping expressions
Must "hook" LHS prior to calling peepholes
* Ch9 Region optimization
Bug fix, GVN hits 2 inProgress Loops
Bug fix lifetime tracking when parsing dead code
Bug fix debug find call
GraphViz post-iterate
* Readme overhaul
Progress on Ch 9 readme
* Fix bugs hashcode
Was relying on label() hashCode for Phi, Proj; since this is debug-only cannot be relied on. Proj relies on _idx field, Phi needs a !inProgress check.
* Constant nodes print "#" before con
* Add a farther neighbor check
Peeps that check more than the nearest neighbor register a dependency on the Node that failed them. Should that Node later change, the peep root is put back on the worklist and revisited.
* Fix addDeps assert
Unwind golden test print, print smarter.
Unlock edges in subsume
* Update README
* shuffle adddeps forward one
its needed again shortly in another test, so just cover it now
* Fix fuzzer bugs
Peep x+(-y) to x-y
Handle TOP inputs; didn't think it could happen before running an optimistic pass, but fuzzer proved me wrong.
Deleting an input can recursively delete the self-node.
When checking the compute() type assert, delay setting _type so the method can just be re-run in the debugger.
Missing addDep in Phi
Parser mis-handling stacked operators like "1+-2" or "1==!=<=<>=>2"
Make Work list deterministic between tests.
* Update fuzzer to run iterate (#62)
* Update fuzzer to run iterate
* Work seed is now reset by reset
* A few more fuzzer tests
Set _type in iter() even later, better debugging.
Handle dead active scopes in visiualizer.
Region ideal honors Loop invariants; finish Region ideal for single input; inProgress check is a little tighter.
Type.isConstant is true strictly for lattice centerline constants. Clean up TypeInteger.
ideaj warning removal
* Fix all fuzzer bugs
iter() does not call peep(), instead peep() is self-recursive. This allows Iterate() to call iter(), and not get into arbitrary recursive peep() changes that do not track on the worklist.
Div, Minus, If all monotonic.
Catch a bunch of progress issues.
Robustify IRPrinter and Iterate and Region ideal
* Reducer could run into an infinite loop (#63)
* Write up how the Evaluator works (#64)
* Write up how the Evaluator works
* Some small improvements and a slightly better wrap up.
* Series of fuzzer bugs.
Fix monotonicity for all data nodes.
Generic compute intercept for data nodes, check all inputs for TOP/BOTTOM, and again for IntDataNodes.
Fix general progress bug allow high Types as constants.
Fix progress Region 1-input has obvious idom.
Make shortcut for fuzzer; renames Fuzzer to not have "Test" in the class name.
Fix invert comment in TypeInteger
* All fuzzer tests pass
Turn off expensive assert accidentally turned on
CSE needs to join types.
Add a type join.
Missing dep in Phi
* More README
* Hacking alternative way to fix the type compute
* Node is no longer IntSupplier
Renamed Work to WorkList
Renamed Iterate to IterOptim
Renamed Node.iter() to Node.peepholeOpt()
WorkList expects elements to be of Node
* Add an example of GVN
* Rename the method depsClear to moveDepsToWorklist - to better capture what it actually does.
* Add a second example of GVN benefits
* Fix typo
* Add example of worklist opt
* Prepare to allow alternative post parse worklist opt
* Alternative WorkList opt that has following differences:
1. It does not require dependencies between nodes
2. It does not require calls from inside the Node class, and therefore runs totally independently as a post parse step.
3. It is simple
* Alternative WorkList opt that has following differences:
1. It does not require dependencies between nodes
2. It does not require calls from inside the Node class, and therefore runs totally independently as a post parse step.
3. It is simple
* The RPO list was incomplete as it only identified the subgraph accessible from the STOP node.
* Fix iter count
* Add test suggested by Xmilia
* Fix bug where after the region is peeped the phis get consistent number of inputs
* Fix bug where after the region is peeped the phis get consistent number of inputs
* Dump out stats on how many nodes we peepd during the post parse iterative opt.
* Make it easy to switch the IterOpt
* Use deps based worklist by default
* Sharper worklist add
* Copy across Cliff's changes
* Merge changes to Iterate
* Revert failing change
* Update readme
* Add comments / update docs to explain the patterns where we call addDep().
* As before, unconditionally made dep a dependent of region.
* Fix a lot of missing dep issues
Rename IterOptim -> IterPeeps
Some grammar changes in comments & readme
* Bump up fuzzer limits, more testing
Missing dep in idom calc in IfNode.
Missed idom cache clear on Region edit.
* Remove RPO based peeps
O(n^2) behavior
* Minor updates README
* fix compile bug
---------
Co-authored-by: Cliff Click <cliffc@acm.org>
Co-authored-by: XmiliaH <45106915+XmiliaH@users.noreply.github.com>
Co-authored-by: Darrick Wiebe <darrickw@untether.ai>
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