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* Restrict subtraction zero peepholes to integer operandspr254-fixesCliff Click2026-09-251-5/+5
| | | | | | Require resolved integer mode in chapter 25 so zero subtraction preserves floating-point signed zero. Keep nonnumeric operands in the graph for subtraction diagnostics. Add signed-zero coverage from chapter 12 and null-subtraction diagnostics from chapter 22. Confirmed the regressions fail on the original PR. Full Make suites pass in chapters 4-25 (5462 tests), including fresh chapter 25 sys.o compilation.
* Add testsfuhsnn2026-09-251-0/+28
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* Extend and backport SubNode peepholefuhsnn2026-09-251-4/+15
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* Keyboard shortcutsCliff Click2026-09-233-1/+13
| | | | | Fast forward/reverse, pick-a-frame. Shorter type names.
* int fallbacks for int opsCliff Click2026-09-227-17/+37
| | | | all chapters, a little sharper for int ops
* Graph cleanupCliff Click2026-09-222-1/+3
| | | | Phis stay with regions, stop sinks to bottom,
* Tidy up scope displayCliff Click2026-09-221-1/+1
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* Add shared graph viewer to all chaptersCliff Click2026-09-2222-346/+150
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* Unify GCM across chaptersCliff Click2026-09-207-74/+88
| | | | | | Remove the _anti field. Remove the isPinned() call. Add a copyEmpty call.
* Unify mixed-return checking and resultsCliff Click2026-09-197-15/+34
| | | | Unify dominator caching.
* Use isDead() instead of checking null inputsCliff Click2026-09-191-2/+2
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* debug printers no longer call self-optimizing accessorsCliff Click2026-09-193-5/+83
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* Handle double-negation preserving not-null knowledgeCliff Click2026-09-192-0/+47
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* Get makefiles and fuzzer testing uniform across chaptersCliff Click2026-09-173-5/+37
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* Fix stale copy-pasted comment on BoolNode's phiCon call (#249)Symious2026-09-091-3/+3
| | | | | | | | | | | | | | | | | | The three comment lines above `AddNode.phiCon(this, ...)` in BoolNode were copy-pasted from MulNode and never adapted: they use `*` as the operator and describe the rotated shape `(x * (phi cons)) * con`. For BoolNode neither is right. The operator is a compare, and in chapters 6-9 `rotate` is hard-coded `false`, so the rotated shape is never matched; the shapes actually handled are `(phi cons) cmp con` and `(phi cons) cmp (phi cons)`. Reword the comment accordingly, and in chapters 6-9 add a line noting why rotate is off. Chapters 10-25 pass `this instanceof EQ`, so no such claim is made there. Comment-only change; no code is touched. Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
* Backport renaming of `Type::_print()` in Chapter13 to earlier chapters (#244)Hsiang-Ying Fu2026-07-038-16/+16
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* Move `addUse()` return statement to `keep()` (#243)Hsiang-Ying Fu2026-07-031-6/+3
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* Op Chaining (#224)Tamás Hadházy2025-08-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * indirect addressing modes * setop change opcode, rename FLOAT_OFFSET * mask sib and modrm with 3 bits, 4th bit goes into rex. * sign extend div with cqo * idiv input is fixed to rax and RMASK, grab input from second slot when encoding * encoding of newx86 * tfp and CallEndNode encoding * sib improvement * more cleanups * more cleanups * Allow a killMap to kill regs. Bugfix scheduler. Bugfix spiller - self-conflict order depended on hashtable iteration order, which depended on System.hashCode which would vary run to run. Improvements to coloring Improvements to spill quality testing * Added flags-kill for XOR * Missing add-deps from fuzzer * Update Chapter14Test.java * fixed order of operands * base rex fixup * more bug fix * remove jukn files * minimal "make release" * further fixes * minor fixes * minor fixes * minor fixes * base != -1 check, precedence fix * Add regkills in IFG building Fix bug LRG union stats Adjust self-conflict splits to be slightly less aggressive In every use-side split, dont split-after-split same block. NewNode is a multi, does not define a register * 64 bit encoding for gpr(s) load * RA improvements Attempt to commute to keep reg-masks compatible. Clones with kills (x86 XOR killing flags to zero) fail before the flag-def. Bugfix failed to color last lrg. More smarts on picking trivial LRGs during coloring Drop isSplit, add SplitNode Pass regalloc round to all splits for debugging Self-conflict no split on loop backedge. Handle split that gets made goes dead No-reg-mask spilling handles case with many def/uses. Add DivIX86 BrainFuck, MergeSort now allocate as testing * 8 bit imm support * conditional jump fix * Push l,ast change, unbreak branch * XOR remove extra opcode, imm size supports 8 bit. * Finally pass the `new [u8]` double-copy test * Fix several ARM reg setup problems Finish Split bypass check ARM: rsp is also a fixed zero, in R31. R0 is a valid register. CallArm prints args, passes TFP for arg selection. Does not return a register. All CallEndARM which DOES return a register. Parms missing tfp for float args. ProjARM after a New missing regs. RetARM missing RPC. Remove hopeful DivIX86 * 64 bit imm for alu ops encoded in extra reg then use it in Op as an operand * Bunch of minor arm, risc fixes small constants not cloning * jump invert encoding * warning comment * Much ARM fixage One More Go-Round with Better Biased Colors Fix bug picking deepest spills to bias. ARM: remove default 2-address. Fix regmask overflow. Rename some ops to be canonical. * Fixes to release Port does not have to be in a Simple named directory. Call convention is just a string, no enum Missed some tests running RISC, ARM. * Minor release change to allow another foreign port * better split encoding and fix CallInMask * notNode * fix callInMask * riscv init * riscv basic ALU ops and types of instructions * Allowing non-Simple repo ports Expanding public API slightly so alternative (non-Simple repo) ports can happen. RegMask supports single-bit-set and a long bitmask. Bugfix GCM splitting multiple global constants. Bugfix LCM grabbing a projection vs multi Bugfix RegAlloc when avoiding splitting a clonable Source code in release More timing in CodeGen * riscv indirect addressing and function calls * Cleanup call ABI presentation Everybody uses the same names, same code shapes * Caller save regs ...not callee save yet * Expose caller save regs * Store Risc adjustments, no imm in MemOpRISC * specific print encoding for cpus * merge fixup * More x86,risc,arm call convention fixes Collect callee and caller save masks (inverts of each other, except for spills). Reorg layout to be closer to each other; remove dead mask definitions; add final keyword * lui fix up with 32 bit immediates * Callee-save registers Callee-save registers and masks and inserting LRGs for same and spilling and picking good spills. Insert CalleeSaveNodes and edges to RetXXXs and RegMasks for those edges. Iterators for regmask. Better printing post-allocation * RegMask supports 128 bits All regs available arm, risc. MergeSort compiles & runs * added flags splitting * Fix risc5 compares No flags on risc5. Branch takes 2 inputs (one can be imm12). Float compare only sets a GPR to 0/1. Bool has a isFloat Common risc5 imm-form handling * extend test cases * imm encoding, flags fixed * grep for Todo: relocs * float riscv fixed * flags for set * lui fix for small bits [0, 12] * arm init * arm last touches * fmov still needs fix * minor fixes * minor fixes(2) * got rid of unnecessary stuff * create ch21 * remove encodings from chapter20 dir * 1/2 pass cleaning up ARM encoding API * ARM encoding compiles * Risc R_TYPE and I_TYPE * Progress RISC encodings Missing lots of stuff still * progress risc encoding * risc encodings compile * Update README.md * Fold up redundant OP/OP-FP risc5 encoding * x86 mem opcodes first cut break out MemOp encodings into parts; change x86 indirectAdr to use Encoding class, remove redundant asserts & code * x86 mem op encodings * x86 reg+imm forms * most reg-reg forms * More x86 encodings * Last few encodings * switch to binary literals over decimals for opcodes * logical immediates fixed, bitwise ops imm forms * tfp and setArm fixed * PC relative float for riscv * readme init * Merged pr/169 * Fixed the array1 test encodings Clean up branch invert logic during BB layout Cleanup branch target printing for RISC,ARM ImmRISC ops mask imm12 to 12 bits Fix NewRISC; hardcode RPC as part of call Fix RISC inverting branchs >,>= * floatarm encoding * tfparm and intarm * uncontional jump encoding for arm and riscv * smarter IntARM, Intx86 does not always include rex. * REX after PREFIX * fixup load and store indirect * updated rex prefix, if its 0x40 then its not needed * Rex fix for floats, got rid of unnecessary stuff. * rename to camel case, better param name * add test export * merged * store opt * store and load optimised forms handled * tfp patch * Store/load float arm/riscv/x64 * got rid of debug print * splits for x86, riscv and arm * readme fixups * fix global symbol numbering for constants * fix TFP pathc on arm and riscv, keep symbols in good order. * fix opcode for store and loads, memOpRisc for Store and splitting * replace hard coded opcodes with major opcodes * replace hard coded opcodes with major opcodes * add asserts and fix reg numbering * add asserts and fix reg numbering * minor updates * revert changes * remove constant pool from encoder TODO: add flag for JIT * extend test cases * minor fixes * minor fixes * update float test case * stringHash fix on x64 * remove conditional ConstantPool write * brainfuck minor fixes * minor arm fixes * split fix * brainfuck and fib * brain fuck * arg_count, person * add ignore * typo * riscv test sieve attempt * minor changes * riscv5 emulator additions * arm eval setup * Update riscv.java * arm eval basics * delta fixes * arm fixes * testfib arm * arg_count * small update for test newton * small update for test newton * testNewton runs on x64, riscv and arm * arm additions * arm pc eval fix * arm workings * debugging * Progress sieve on ARM Most ops need WMASK as the output, to exclude RSP. calloc sentinal changes to multiple of 4 NewArm needs to set arg X0 to #1; arg X1 is length. Fix EvalARM calling calloc & not advancing PC. Fix EvalARM using ints vs longs. Fix EvalARM missing AndI encoding. * Fix some arm encoding Fix some OBOB in R5 calloc encoding. Sort EvalArm by major opcodes. Add ASL. Remove leading switch. Fix OBOB in calloc. Fix shift in ld/st with reg+offset * arm sieve test * test person push * brainFuck arm * "and" "or" syntactic sugar * update encoding * ch23 `and` `or` * hack parse trinary for and, or * close * fixed or issue * Update CallEndNode.java * fix type issue * fixed * Adjust parseTrinary precedence vs && || * Fix arm simulation return * Formatting * Formatting * simplify rn to be always 0. * ch24 init * stacked rel * stack init * stack rel * remove parenthesis * got rid of old test case * update * upgrade eval * arm encoding bugs encodeing cset had a shift wrong eval missed using 0 for r31 * remove debug prints * force main to encode first * fix for missing main * got rid of debug prints * backwards with ch23 --------- Co-authored-by: Cliff Click <cliffc@acm.org>
* Cleanup (#162)RobertObkircher2025-02-162-6/+6
| | | | | | | | | * remove unused method lazyFRef * remove unused method copyF(Node, Node) * make TypeMemPtr constants final * make ConstantNode value final
* Ch19 (#155)Cliff Click2025-02-071-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Initial push Major CodeGen cleanup; most static globals move into the CodeGen object. * Minor progress bug with mutual recursion * Add test from pr#148 * First cut x86 "port" Only "return 0;", no registers, no encoding, but yah gotta start somewhere * Update README.md * Update README.md * Update ListScheduler.java * command line launcher for simple Parser bug fref in args Some new test cases. * Add basic RegMask for more than 64 bits of register mask. Add calling convention basics to X86; con+ret RegMasks. GCM computes CFG for all users. Drop unused MultiUse. Pick up reg-pressure aware ListScheduler. Re-layout CodeGen file to get code & data chunks nearer each other. minor Ary extension * ASM Printer InstSel handles folding 2+ ideal ops into 1 machine op * handle instSel for some control flow Bool,If,CProj,Region,Phi Handle 2-op expansions Shuffle instSel graph walk back again. * Basic if-block inst selects and asm prints * Add mul-by-coinstant to shift * left shift codegen basic * exclude RSP from *write* mask * 2-arg add (not immediate) mul-by-small constant opt. Some utilities. * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * inst select for new struct allocation * Float, bitwise and arithmetic operands codegen x86-64 (#150) * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * float ops without imm values * merge * merge * inst select for new struct allocation * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * float ops without imm values * merge * merge * Rebased on ch 19 * Update tests --------- Co-authored-by: Cliff Click <cliffc@acm.org> * cleanup after merge alpha-sort helper fcns implicit test vs zero/null * Add LEA op asm print works on ideal nodes for all tests * Minor cleanup lea * x86 addressing modes during inst select Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores. Basic load/store for now, op-to-mem comes later add same becomes Shl by 1. Drop DivF-immiedate * extended ch13, 14,15,16 (#153) * merge2 * merge3 * Fix a few minor fuzzer bugs * Force array layout ld/st get size (but not signed/unsigned) Add unsigned LT for later range checks. * Fix a bunch of float issues was deleting required inputs * simpler invariant defensive copy inputs for simpler invariant in complex sharing patterns inc/dec form (just the opcode now). * Call & CallR X86 instructions * Add-from-memory op Remove FP immediate forms. * Remove name from TFP Never shoulda been there (but was convenient for awhile). Moved into FunNode, found by checking the linker table with a TFP. * New (#154) * merge2 * merge3 * GCM for float ops fixed, other cleanup - small extensions * call setup * merge2 * remove debug prints add check for bad call convention fix 3 tests (bad merge?) * cleanup call convention abi Needs more love at some point... * one more cleanup ABI --------- Co-authored-by: Cliff Click <cliffc@acm.org> * Add CmpMem form Common addressing mode print LEA can skip a base * Add a AddFMemX86 A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns. * Docs * XMM reg mask fix Minor README updates * Allow inverted cmp/mem narrowing stores can bypass an AndMask Array length loads do not need control Some missing print info * Support "*ptr op= val" at least for MemAdd * missed golden rule update * Array len is u32 load-after-store zero/sign-extends if the store is truncating * One more missed case --------- Co-authored-by: hadha <helsgithub15@gmail.com> Co-authored-by: Tamás Hadházy <85063808+Hels15@users.noreply.github.com>
* Add testRedeclareVar in all later chapterstannal2025-01-191-0/+10
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* Test for "arg--2"Cliff Click2025-01-151-0/+6
| | | | Parse as "arg - -2" and not "arg-- 2" which is a syntax error
* Link to linear history and tag chaptersThalia Archibald2024-10-231-0/+2
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* review comment fixesCliff Click2024-10-211-0/+34
| | | | | TODO for GraphViz Remove dead code
* more grammar cleanupCliff Click2024-10-131-1/+1
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* Turn off all printing during test runsCliff Click2024-10-1211-139/+122
| | | | was making 10000 lines of ignored output
* fix typo ch 11Cliff Click2024-10-061-1/+1
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* remove peephole from ProjNode::idealize that is already handled by computeRobert Obkircher2024-09-161-10/+7
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* move x-x check up frontCliff Click2024-09-131-3/+4
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* x-x==0Cliff Click2024-09-132-5/+9
| | | | | | Move x-x==0 to compute. Add x/1 ==> x All chapters
* Fix GCM of CSE storesCliff Click2024-09-126-15/+28
| | | | | Stop CSE of stores. Backports to ch11,12,13,14
* Backport empty statement fixCliff Click2024-09-071-0/+1
| | | | | Split Ch13 tests from Chapter12Test.java Handle forward refs never defined.
* Ref types workingCliff Click2024-08-061-5/+0
| | | | | | | | | GCM uses a breadth-first pass for schedule-late instead of a post-order; the post-order walk depends on StoreNodes being pinned, which is true in C2 but not Simple. Move GCM call out of IterPeeps. Struct field init is "makeInit()" not integer zero. Rename Type._print to print. Store,Load prints include field name.
* Fix grammar and forward-port minor changes (#91)Thalia Archibald2024-07-0120-122/+109
| | | | | | | | | | | | | | | * Backport test exception handling to chapter 1 * Add unary ! to chapter 10 and 11 grammars * Lex { } ! as punctuation * Forward-port format whitespace * Forward-port test organization * Forward-port replace build-graphs.sh with Makefile * Add chapter title to chapter 11
* #85 #80 missed details (#90)Dibyendu Majumdar2024-06-301-0/+29
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* #80 #85 apply bug fixes from chapter10 (#89)Dibyendu Majumdar2024-06-3021-173/+210
| | | | | | | | | | | | | * #80 #85 apply bug fixes from chapter10 * #85 #80 more detail regarding anti-dependency * Remove Util.eq Was enforced interning of strings, not needed here. --------- Co-authored-by: Cliff Click <cliffc@acm.org>
* Cliff's GCM implementation for chapter 11 (#88)Dibyendu Majumdar2024-06-3085-0/+13925
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