From b68dafa3e6e231bd0d0b0e613986c7e3181349b9 Mon Sep 17 00:00:00 2001 From: Cliff Click Date: Thu, 10 Apr 2025 13:47:06 -0700 Subject: More README updates --- chapter19/README.md | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'chapter19') diff --git a/chapter19/README.md b/chapter19/README.md index 752e139f..0d8e481f 100644 --- a/chapter19/README.md +++ b/chapter19/README.md @@ -38,8 +38,8 @@ implementation at least the ability to add CPU ports lazily. ## Machine Specific Nodes -We add a notion of "machine specific" Nodes, which implement the `Mach` -interface. `Mach` nodes define incoming and outgoing registers for every +We add a notion of "machine specific" Nodes, which implement the `MachNode` +interface. `MachNode` nodes define incoming and outgoing registers for every instruction, their bit encodings and user representations. Later we'll add function unit information for a better local schedule. @@ -124,11 +124,11 @@ E.g `lea` is not present. ### Branching -In `x86_64_v2`, branching requires a comparison instruction to set flags, -followed by a jump instruction that uses those flags. -In contrast, RISC-V includes all necessary operands within the -branch instruction itself, eliminating the need for a separate -comparison step. + +In `x86_64_v2`, branching requires a comparison instruction to set flags, +followed by a jump instruction that uses those flags. In contrast, RISC-V +includes all necessary operands within the branch instruction itself, +eliminating the need for a separate comparison step. E.g ``` @@ -136,9 +136,10 @@ beq x10, x11, some_label ``` `CBranchRISC` implements this behavior. + ### No R-Flags -No R-flags exist in RiSC-V. To obtain similar functionality: +No R-flags exist in RiSC-V. To obtain similar functionality: We can set the value of registers based on the result of the comparison this way explicitly. ``` xor a0, a0, a1 @@ -149,8 +150,9 @@ The `seqz` instruction will set `a0` to 1 if `a0` is zero from the previous oper This matches `SetRISC` in the `nodes/cpus/riscv` port. ### Fixed instruction length -RISC-V instructions have fixed length of 32 bits(in most cases) which means that we can benefit -from displacements in the encoding side. + +RISC-V instructions have fixed length of 32 bits(in most cases) which means +that we can benefit from displacements in the encoding side. E.g ``` -- cgit v1.2.3