From 2370fb29d4538479af9eb94fc666a5ce09fcb492 Mon Sep 17 00:00:00 2001 From: Cliff Click Date: Sat, 8 Mar 2025 09:59:31 -0800 Subject: Ch20 reg (#166) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * READMEs * Update README.md * Update README.md * Move printing into print dir * Move codegen into codegen * Framework for Reg Alloc * First cut BuildLRG RegMask.EMPTY -> null * Setup for first simple split * First cut split code for mismatch regs * Live Ranges U-F BuildLRG for Phi Add CmpFX86 * FPR return CallEndX86 needed to tell fp return from gpr ret Call has no output regs. * Next cut regalloc Building IFG. Coloring. Some nested spilling Optimize divf/con -> mul times inverse * RISC-V basic isel (#156) * Initial push Major CodeGen cleanup; most static globals move into the CodeGen object. * Minor progress bug with mutual recursion * Add test from pr#148 * First cut x86 "port" Only "return 0;", no registers, no encoding, but yah gotta start somewhere * Update README.md * Update README.md * Update ListScheduler.java * command line launcher for simple Parser bug fref in args Some new test cases. * Add basic RegMask for more than 64 bits of register mask. Add calling convention basics to X86; con+ret RegMasks. GCM computes CFG for all users. Drop unused MultiUse. Pick up reg-pressure aware ListScheduler. Re-layout CodeGen file to get code & data chunks nearer each other. minor Ary extension * ASM Printer InstSel handles folding 2+ ideal ops into 1 machine op * handle instSel for some control flow Bool,If,CProj,Region,Phi Handle 2-op expansions Shuffle instSel graph walk back again. * Basic if-block inst selects and asm prints * Add mul-by-coinstant to shift * left shift codegen basic * exclude RSP from *write* mask * 2-arg add (not immediate) mul-by-small constant opt. Some utilities. * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * inst select for new struct allocation * Float, bitwise and arithmetic operands codegen x86-64 (#150) * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * float ops without imm values * merge * merge * inst select for new struct allocation * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * float ops without imm values * merge * merge * Rebased on ch 19 * Update tests --------- Co-authored-by: Cliff Click * cleanup after merge alpha-sort helper fcns implicit test vs zero/null * Add LEA op asm print works on ideal nodes for all tests * Minor cleanup lea * merge2 * merge3 * GCM for float ops fixed, other cleanup - small extensions * x86 addressing modes during inst select Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores. Basic load/store for now, op-to-mem comes later add same becomes Shl by 1. Drop DivF-immiedate * call setup * extended ch13, 14,15,16 (#153) * merge2 * merge3 * Fix a few minor fuzzer bugs * Force array layout ld/st get size (but not signed/unsigned) Add unsigned LT for later range checks. * Fix a bunch of float issues was deleting required inputs * simpler invariant defensive copy inputs for simpler invariant in complex sharing patterns inc/dec form (just the opcode now). * Call & CallR X86 instructions * merge2 * Add-from-memory op Remove FP immediate forms. * Remove name from TFP Never shoulda been there (but was convenient for awhile). Moved into FunNode, found by checking the linker table with a TFP. * remove debug prints add check for bad call convention fix 3 tests (bad merge?) * cleanup call convention abi Needs more love at some point... * one more cleanup ABI * New (#154) * merge2 * merge3 * GCM for float ops fixed, other cleanup - small extensions * call setup * merge2 * remove debug prints add check for bad call convention fix 3 tests (bad merge?) * cleanup call convention abi Needs more love at some point... * one more cleanup ABI --------- Co-authored-by: Cliff Click * Add CmpMem form Common addressing mode print LEA can skip a base * Add a AddFMemX86 A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns. * Docs * XMM reg mask fix Minor README updates * Allow inverted cmp/mem narrowing stores can bypass an AndMask Array length loads do not need control Some missing print info * Support "*ptr op= val" at least for MemAdd * missed golden rule update * Array len is u32 load-after-store zero/sign-extends if the store is truncating * One more missed case * riscv init * added not imm form bitwise shifts and ops plus test cases * addressing modes(high chance it'll get deleted) * fix minor bug * delete non existing matches * replace RegMask.Empty with null * riscv handle store and load, fltRisch uses risc reg now * load float into GPR and then later in RA do hard split. * minor changes * turn off ch20 tests * Update Chapter20Test.java --------- Co-authored-by: Cliff Click * Bring pr/154 to ch 20 RISC5 changes. Some missing x86 ops. Still needs some calling convention love. * First cut regalloc working Biased coloring; tracking splits around a LRG. Separate split for self-conflicts. postColor to remove junk splits. Some minor riscv fixes. * Compile some riscv codes If SplitEmptyMask does not apply, fall back to normal split. Missing CmpFRISC. Renamed riscv flags. RetRISC handls FPR remove extra RegMask constructurs * Progress reg alloc Handle multi-node projections. A little smarter about 2-addr scheduling RegAlloc must-have single registers removes from other masks instead of interfering; had the mask removal backwards in a few cases. LRG/RegMask COW expand masks before mutating. Clone small constants instead of spilling. Alloc & ProjX86 get output reg masks. Full print large reg masks with sp+offset * UF LRGs can be null during coloring * Finish UF find * README updates * Fix ch19 mis-merge? * x86 call args, risc5 load/store regs * Push RISC WMASK avoid writing to RSP * Progress calling convention allocations Call unlinks before reg alloc. CallEnd tracks RPC CallX86 requires TFP for correct ABI Bias Color tracks 2-addr. RPC gets a mask/stack-slot Clean up call/fun ABI Fix mask RET, RET_F Fix print stack slot Remove isMultiHead, isMultiTail Better all-asm print * Beef up Newton test * Clean pass normal tests New fcn print upgrades several golden rule tests. Move the unlink-all from the walk::err call (which IS used during IterPeeps) to GCM. CallEnd upgrades return type based on constant call. Fix unlink to also unlink CallEnd Constant TFP print checks constant Tested an untested Load * Arm basics, minor changes in riscv (#160) * Initial push Major CodeGen cleanup; most static globals move into the CodeGen object. * Minor progress bug with mutual recursion * Add test from pr#148 * First cut x86 "port" Only "return 0;", no registers, no encoding, but yah gotta start somewhere * Update README.md * Update README.md * Update ListScheduler.java * command line launcher for simple Parser bug fref in args Some new test cases. * Add basic RegMask for more than 64 bits of register mask. Add calling convention basics to X86; con+ret RegMasks. GCM computes CFG for all users. Drop unused MultiUse. Pick up reg-pressure aware ListScheduler. Re-layout CodeGen file to get code & data chunks nearer each other. minor Ary extension * ASM Printer InstSel handles folding 2+ ideal ops into 1 machine op * handle instSel for some control flow Bool,If,CProj,Region,Phi Handle 2-op expansions Shuffle instSel graph walk back again. * Basic if-block inst selects and asm prints * Add mul-by-coinstant to shift * left shift codegen basic * exclude RSP from *write* mask * 2-arg add (not immediate) mul-by-small constant opt. Some utilities. * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * inst select for new struct allocation * Float, bitwise and arithmetic operands codegen x86-64 (#150) * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * float ops without imm values * merge * merge * inst select for new struct allocation * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * float ops without imm values * merge * merge * Rebased on ch 19 * Update tests --------- Co-authored-by: Cliff Click * cleanup after merge alpha-sort helper fcns implicit test vs zero/null * Add LEA op asm print works on ideal nodes for all tests * Minor cleanup lea * merge2 * merge3 * GCM for float ops fixed, other cleanup - small extensions * x86 addressing modes during inst select Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores. Basic load/store for now, op-to-mem comes later add same becomes Shl by 1. Drop DivF-immiedate * call setup * extended ch13, 14,15,16 (#153) * merge2 * merge3 * Fix a few minor fuzzer bugs * Force array layout ld/st get size (but not signed/unsigned) Add unsigned LT for later range checks. * Fix a bunch of float issues was deleting required inputs * simpler invariant defensive copy inputs for simpler invariant in complex sharing patterns inc/dec form (just the opcode now). * Call & CallR X86 instructions * merge2 * Add-from-memory op Remove FP immediate forms. * Remove name from TFP Never shoulda been there (but was convenient for awhile). Moved into FunNode, found by checking the linker table with a TFP. * remove debug prints add check for bad call convention fix 3 tests (bad merge?) * cleanup call convention abi Needs more love at some point... * one more cleanup ABI * New (#154) * merge2 * merge3 * GCM for float ops fixed, other cleanup - small extensions * call setup * merge2 * remove debug prints add check for bad call convention fix 3 tests (bad merge?) * cleanup call convention abi Needs more love at some point... * one more cleanup ABI --------- Co-authored-by: Cliff Click * Add CmpMem form Common addressing mode print LEA can skip a base * Add a AddFMemX86 A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns. * Docs * XMM reg mask fix Minor README updates * Allow inverted cmp/mem narrowing stores can bypass an AndMask Array length loads do not need control Some missing print info * Support "*ptr op= val" at least for MemAdd * missed golden rule update * Array len is u32 load-after-store zero/sign-extends if the store is truncating * One more missed case * riscv init * added not imm form bitwise shifts and ops plus test cases * addressing modes(high chance it'll get deleted) * fix minor bug * delete non existing matches * replace RegMask.Empty with null * riscv handle store and load, fltRisch uses risc reg now * load float into GPR and then later in RA do hard split. * minor changes * turn off ch20 tests * Update Chapter20Test.java * add riscv port to readme * arm init * work in progress * arm2 bs * work in progress * clearnup arm * fixed main pr problems * regmask extra comments --------- Co-authored-by: Cliff Click * Update Chapter20Test.java * Weaken range-check test since no range checks... test cannot fail (pass) * Fix issue #161 Error adding 'null' and '5' * bug fixs, cloning constants Fix bug missing Find. Fix bug setDef does unordered removal from basic blocks. Use cloned constants for spilling. * RA fixes SplitSelfConflict MUST split before uses and after defs. Split global constants across functions Missing find in union; Inserting split after new inserted wrong place Pre-remove null LRGs before color. Bias color hunts through Phis Shorten InstructionSelection. Rename !unified() to leader() AddMemX86 is 2-addr Add CastXXX to preserve register across cast. * Allow a killMap to kill regs. Bugfix scheduler. Bugfix spiller - self-conflict order depended on hashtable iteration order, which depended on System.hashCode which would vary run to run. Improvements to coloring Improvements to spill quality testing * Added flags-kill for XOR * Missing add-deps from fuzzer * Update Chapter14Test.java * remove jukn files * minimal "make release" * Add regkills in IFG building Fix bug LRG union stats Adjust self-conflict splits to be slightly less aggressive In every use-side split, dont split-after-split same block. NewNode is a multi, does not define a register * RA improvements Attempt to commute to keep reg-masks compatible. Clones with kills (x86 XOR killing flags to zero) fail before the flag-def. Bugfix failed to color last lrg. More smarts on picking trivial LRGs during coloring Drop isSplit, add SplitNode Pass regalloc round to all splits for debugging Self-conflict no split on loop backedge. Handle split that gets made goes dead No-reg-mask spilling handles case with many def/uses. Add DivIX86 BrainFuck, MergeSort now allocate as testing * Push l,ast change, unbreak branch * Finally pass the `new [u8]` double-copy test * Fix several ARM reg setup problems Finish Split bypass check ARM: rsp is also a fixed zero, in R31. R0 is a valid register. CallArm prints args, passes TFP for arg selection. Does not return a register. All CallEndARM which DOES return a register. Parms missing tfp for float args. ProjARM after a New missing regs. RetARM missing RPC. Remove hopeful DivIX86 * Bunch of minor arm, risc fixes small constants not cloning * Much ARM fixage One More Go-Round with Better Biased Colors Fix bug picking deepest spills to bias. ARM: remove default 2-address. Fix regmask overflow. Rename some ops to be canonical. * Fixes to release Port does not have to be in a Simple named directory. Call convention is just a string, no enum Missed some tests running RISC, ARM. * Minor release change to allow another foreign port * Allowing non-Simple repo ports Expanding public API slightly so alternative (non-Simple repo) ports can happen. RegMask supports single-bit-set and a long bitmask. Bugfix GCM splitting multiple global constants. Bugfix LCM grabbing a projection vs multi Bugfix RegAlloc when avoiding splitting a clonable Source code in release More timing in CodeGen * Cleanup call ABI presentation Everybody uses the same names, same code shapes * Caller save regs ...not callee save yet * Expose caller save regs * More x86,risc,arm call convention fixes Collect callee and caller save masks (inverts of each other, except for spills). Reorg layout to be closer to each other; remove dead mask definitions; add final keyword * Callee-save registers Callee-save registers and masks and inserting LRGs for same and spilling and picking good spills. Insert CalleeSaveNodes and edges to RetXXXs and RegMasks for those edges. Iterators for regmask. Better printing post-allocation * RegMask supports 128 bits All regs available arm, risc. MergeSort compiles & runs * Fix risc5 compares No flags on risc5. Branch takes 2 inputs (one can be imm12). Float compare only sets a GPR to 0/1. Bool has a isFloat Common risc5 imm-form handling * yank MulIRISC * fix arg flags reg Arm split op can spill flags bugfix RegAlloc 1st real >=64bit reg num * Update Chapter20Test.java * Turn off transpile tests which are broken for some time now * A lot more readme * better flags ListScheduler stalls cmp/jmp in the same block; avoids some flags spills. Make CmpIX86/ARM rematieralize. Bugfix: remove some include x86/risc/arm in other dirs. Canonicalize boilerplate fcn order * regalloc improves Use FltRISC, not clonable requires a spill from int->flt regs. new splits track origin LRG, so later splits in the same pass know what lrg a spilled input is. * RA improvements & fixes Bugfix on split loop-depth computation. Track killmask kills, which are always capacity kills and require more spilling. Rename the riscv registers canonically, so I can tell them part! Definitely no GP or TP in Simple. Node insertAfter bypass a little more conservative. * RA bugfix remove unified failed live ranges * easier access for remote ports debug support * Lots more comments * bugfix infinite peep cycle on (17 ^ 3.14), i.e. bad program * Fix imm12 shift --------- Co-authored-by: Tamás Hadházy <85063808+Hels15@users.noreply.github.com> --- chapter20/Makefile | 12 +- chapter20/README.md | 428 ++++++++++++++++- chapter20/docs/ifg_trim.pdf | Bin 0 -> 155190 bytes chapter20/docs/pardoe.docx | Bin 0 -> 22583 bytes .../java/com/seaofnodes/simple/ASMPrinter.java | 140 ------ .../src/main/java/com/seaofnodes/simple/Ary.java | 19 +- .../main/java/com/seaofnodes/simple/CodeGen.java | 288 ------------ .../com/seaofnodes/simple/GlobalCodeMotion.java | 241 ---------- .../com/seaofnodes/simple/GraphVisualizer.java | 288 ------------ .../main/java/com/seaofnodes/simple/IRPrinter.java | 279 ----------- .../main/java/com/seaofnodes/simple/IterPeeps.java | 9 +- .../main/java/com/seaofnodes/simple/JSViewer.java | 402 ---------------- .../java/com/seaofnodes/simple/ListScheduler.java | 231 --------- .../main/java/com/seaofnodes/simple/Machine.java | 21 - .../main/java/com/seaofnodes/simple/Parser.java | 6 +- .../main/java/com/seaofnodes/simple/RegMask.java | 39 -- .../src/main/java/com/seaofnodes/simple/SB.java | 1 - .../com/seaofnodes/simple/SimpleWebSocket.java | 148 ------ .../com/seaofnodes/simple/codegen/BuildLRG.java | 91 ++++ .../com/seaofnodes/simple/codegen/CodeGen.java | 338 +++++++++++++ .../simple/codegen/GlobalCodeMotion.java | 281 +++++++++++ .../java/com/seaofnodes/simple/codegen/IFG.java | 521 +++++++++++++++++++++ .../java/com/seaofnodes/simple/codegen/LRG.java | 220 +++++++++ .../seaofnodes/simple/codegen/ListScheduler.java | 258 ++++++++++ .../com/seaofnodes/simple/codegen/Machine.java | 22 + .../com/seaofnodes/simple/codegen/RegAlloc.java | 502 ++++++++++++++++++++ .../com/seaofnodes/simple/codegen/RegMask.java | 142 ++++++ .../java/com/seaofnodes/simple/node/AddNode.java | 9 + .../java/com/seaofnodes/simple/node/AndNode.java | 9 +- .../java/com/seaofnodes/simple/node/BoolNode.java | 10 +- .../java/com/seaofnodes/simple/node/CFGNode.java | 25 +- .../java/com/seaofnodes/simple/node/CProjNode.java | 2 +- .../com/seaofnodes/simple/node/CallEndNode.java | 24 +- .../java/com/seaofnodes/simple/node/CallNode.java | 29 +- .../com/seaofnodes/simple/node/CalleeSaveNode.java | 25 + .../java/com/seaofnodes/simple/node/CastNode.java | 8 +- .../com/seaofnodes/simple/node/ConstantNode.java | 8 +- .../java/com/seaofnodes/simple/node/CtrlNode.java | 2 +- .../java/com/seaofnodes/simple/node/DivFNode.java | 11 +- .../java/com/seaofnodes/simple/node/FunNode.java | 25 +- .../java/com/seaofnodes/simple/node/IfNode.java | 6 +- .../java/com/seaofnodes/simple/node/LoadNode.java | 4 +- .../com/seaofnodes/simple/node/LogicalNode.java | 4 +- .../seaofnodes/simple/node/MachConcreteNode.java | 2 +- .../java/com/seaofnodes/simple/node/MachNode.java | 18 +- .../com/seaofnodes/simple/node/MemMergeNode.java | 1 + .../java/com/seaofnodes/simple/node/MemOpNode.java | 10 +- .../java/com/seaofnodes/simple/node/MulNode.java | 6 + .../java/com/seaofnodes/simple/node/NeverNode.java | 2 +- .../main/java/com/seaofnodes/simple/node/Node.java | 104 +++- .../java/com/seaofnodes/simple/node/PhiNode.java | 5 +- .../java/com/seaofnodes/simple/node/ProjNode.java | 1 - .../com/seaofnodes/simple/node/RegionNode.java | 4 +- .../com/seaofnodes/simple/node/ReturnNode.java | 3 +- .../java/com/seaofnodes/simple/node/ScopeNode.java | 1 + .../java/com/seaofnodes/simple/node/SplitNode.java | 22 + .../java/com/seaofnodes/simple/node/StartNode.java | 5 +- .../java/com/seaofnodes/simple/node/StopNode.java | 2 +- .../java/com/seaofnodes/simple/node/XCtrlNode.java | 3 +- .../seaofnodes/simple/node/cpus/arm/AddARM.java | 34 ++ .../seaofnodes/simple/node/cpus/arm/AddFARM.java | 31 ++ .../seaofnodes/simple/node/cpus/arm/AddIARM.java | 51 ++ .../seaofnodes/simple/node/cpus/arm/AndARM.java | 38 ++ .../seaofnodes/simple/node/cpus/arm/AndIARM.java | 56 +++ .../seaofnodes/simple/node/cpus/arm/AsrARM.java | 40 ++ .../seaofnodes/simple/node/cpus/arm/AsrIARM.java | 41 ++ .../seaofnodes/simple/node/cpus/arm/BranchARM.java | 48 ++ .../seaofnodes/simple/node/cpus/arm/CallARM.java | 45 ++ .../simple/node/cpus/arm/CallEndARM.java | 35 ++ .../seaofnodes/simple/node/cpus/arm/CallRRARM.java | 32 ++ .../seaofnodes/simple/node/cpus/arm/CmpARM.java | 30 ++ .../seaofnodes/simple/node/cpus/arm/CmpFARM.java | 31 ++ .../seaofnodes/simple/node/cpus/arm/CmpIARM.java | 54 +++ .../seaofnodes/simple/node/cpus/arm/CmpMemARM.java | 4 + .../seaofnodes/simple/node/cpus/arm/DivARM.java | 33 ++ .../seaofnodes/simple/node/cpus/arm/DivFARM.java | 30 ++ .../seaofnodes/simple/node/cpus/arm/FloatARM.java | 36 ++ .../seaofnodes/simple/node/cpus/arm/FunARM.java | 21 + .../seaofnodes/simple/node/cpus/arm/I2F8ARM.java | 29 ++ .../seaofnodes/simple/node/cpus/arm/IntARM.java | 38 ++ .../seaofnodes/simple/node/cpus/arm/LoadARM.java | 37 ++ .../seaofnodes/simple/node/cpus/arm/LslARM.java | 41 ++ .../seaofnodes/simple/node/cpus/arm/LslIARM.java | 42 ++ .../seaofnodes/simple/node/cpus/arm/LsrARM.java | 40 ++ .../seaofnodes/simple/node/cpus/arm/LsrIARM.java | 41 ++ .../seaofnodes/simple/node/cpus/arm/MemOpARM.java | 58 +++ .../seaofnodes/simple/node/cpus/arm/MulARM.java | 34 ++ .../seaofnodes/simple/node/cpus/arm/MulFARM.java | 30 ++ .../seaofnodes/simple/node/cpus/arm/MulIARM.java | 43 ++ .../seaofnodes/simple/node/cpus/arm/NewARM.java | 31 ++ .../com/seaofnodes/simple/node/cpus/arm/OrARM.java | 42 ++ .../seaofnodes/simple/node/cpus/arm/OrIARM.java | 40 ++ .../seaofnodes/simple/node/cpus/arm/ParmARM.java | 25 + .../seaofnodes/simple/node/cpus/arm/ProjARM.java | 23 + .../seaofnodes/simple/node/cpus/arm/RetARM.java | 49 ++ .../seaofnodes/simple/node/cpus/arm/SetARM.java | 41 ++ .../seaofnodes/simple/node/cpus/arm/SplitARM.java | 22 + .../seaofnodes/simple/node/cpus/arm/StoreARM.java | 52 ++ .../seaofnodes/simple/node/cpus/arm/SubARM.java | 30 ++ .../seaofnodes/simple/node/cpus/arm/SubFARM.java | 32 ++ .../seaofnodes/simple/node/cpus/arm/TFPARM.java | 37 ++ .../seaofnodes/simple/node/cpus/arm/XorARM.java | 41 ++ .../seaofnodes/simple/node/cpus/arm/XorIARM.java | 43 ++ .../com/seaofnodes/simple/node/cpus/arm/arm.java | 385 +++++++++++++++ .../com/seaofnodes/simple/node/cpus/arm/i2f8.java | 4 + .../simple/node/cpus/riscv/AddFRISC.java | 30 ++ .../simple/node/cpus/riscv/AddIRISC.java | 11 + .../seaofnodes/simple/node/cpus/riscv/AddRISC.java | 29 ++ .../simple/node/cpus/riscv/AndIRISC.java | 11 + .../seaofnodes/simple/node/cpus/riscv/AndRISC.java | 38 ++ .../simple/node/cpus/riscv/BranchRISC.java | 47 ++ .../simple/node/cpus/riscv/CallEndRISC.java | 35 ++ .../simple/node/cpus/riscv/CallRISC.java | 44 ++ .../simple/node/cpus/riscv/CallRRISC.java | 35 ++ .../simple/node/cpus/riscv/CastRISC.java | 18 + .../simple/node/cpus/riscv/DivFRISC.java | 30 ++ .../seaofnodes/simple/node/cpus/riscv/DivRISC.java | 32 ++ .../seaofnodes/simple/node/cpus/riscv/FltRISC.java | 31 ++ .../seaofnodes/simple/node/cpus/riscv/FunRISC.java | 21 + .../simple/node/cpus/riscv/I2F8RISC.java | 30 ++ .../seaofnodes/simple/node/cpus/riscv/ImmRISC.java | 40 ++ .../seaofnodes/simple/node/cpus/riscv/IntRISC.java | 35 ++ .../simple/node/cpus/riscv/LoadRISC.java | 40 ++ .../simple/node/cpus/riscv/MemOpRISC.java | 57 +++ .../simple/node/cpus/riscv/MulFRISC.java | 30 ++ .../seaofnodes/simple/node/cpus/riscv/MulRISC.java | 32 ++ .../seaofnodes/simple/node/cpus/riscv/NewRISC.java | 29 ++ .../seaofnodes/simple/node/cpus/riscv/OrIRISC.java | 11 + .../seaofnodes/simple/node/cpus/riscv/OrRISC.java | 39 ++ .../simple/node/cpus/riscv/ParmRISC.java | 26 + .../simple/node/cpus/riscv/ProjRISC.java | 25 + .../seaofnodes/simple/node/cpus/riscv/RetRISC.java | 48 ++ .../simple/node/cpus/riscv/SetFRISC.java | 33 ++ .../simple/node/cpus/riscv/SetIRISC.java | 17 + .../seaofnodes/simple/node/cpus/riscv/SetRISC.java | 33 ++ .../simple/node/cpus/riscv/SllIRISC.java | 11 + .../seaofnodes/simple/node/cpus/riscv/SllRISC.java | 37 ++ .../simple/node/cpus/riscv/SplitRISC.java | 21 + .../simple/node/cpus/riscv/SraIRISC.java | 11 + .../seaofnodes/simple/node/cpus/riscv/SraRISC.java | 38 ++ .../simple/node/cpus/riscv/SrlIRISC.java | 11 + .../seaofnodes/simple/node/cpus/riscv/SrlRISC.java | 38 ++ .../simple/node/cpus/riscv/StoreRISC.java | 56 +++ .../simple/node/cpus/riscv/SubFRISC.java | 30 ++ .../seaofnodes/simple/node/cpus/riscv/SubRISC.java | 29 ++ .../seaofnodes/simple/node/cpus/riscv/TFPRISC.java | 39 ++ .../simple/node/cpus/riscv/XorIRISC.java | 11 + .../seaofnodes/simple/node/cpus/riscv/XorRISC.java | 41 ++ .../seaofnodes/simple/node/cpus/riscv/riscv.java | 361 ++++++++++++++ .../simple/node/cpus/x86_64_v2/AddFMemX86.java | 14 +- .../simple/node/cpus/x86_64_v2/AddFX86.java | 4 + .../simple/node/cpus/x86_64_v2/AddIX86.java | 2 + .../simple/node/cpus/x86_64_v2/AddMemX86.java | 7 +- .../simple/node/cpus/x86_64_v2/AddX86.java | 6 +- .../simple/node/cpus/x86_64_v2/AndIX86.java | 2 + .../simple/node/cpus/x86_64_v2/AndX86.java | 34 ++ .../simple/node/cpus/x86_64_v2/CallEndX86.java | 35 ++ .../simple/node/cpus/x86_64_v2/CallRX86.java | 20 +- .../simple/node/cpus/x86_64_v2/CallX86.java | 21 +- .../simple/node/cpus/x86_64_v2/CastX86.java | 18 + .../simple/node/cpus/x86_64_v2/CmpFX86.java | 29 ++ .../simple/node/cpus/x86_64_v2/CmpIX86.java | 18 +- .../simple/node/cpus/x86_64_v2/CmpMemX86.java | 4 +- .../simple/node/cpus/x86_64_v2/CmpX86.java | 2 + .../simple/node/cpus/x86_64_v2/DivFX86.java | 2 + .../simple/node/cpus/x86_64_v2/DivX86.java | 14 +- .../simple/node/cpus/x86_64_v2/FltX86.java | 13 +- .../simple/node/cpus/x86_64_v2/FunX86.java | 7 +- .../simple/node/cpus/x86_64_v2/I2f8X86.java | 2 + .../simple/node/cpus/x86_64_v2/IntX86.java | 26 +- .../simple/node/cpus/x86_64_v2/JmpX86.java | 8 +- .../simple/node/cpus/x86_64_v2/LeaX86.java | 2 + .../simple/node/cpus/x86_64_v2/LoadX86.java | 6 +- .../simple/node/cpus/x86_64_v2/MemAddX86.java | 6 +- .../simple/node/cpus/x86_64_v2/MemOpX86.java | 18 +- .../simple/node/cpus/x86_64_v2/MulFX86.java | 4 + .../simple/node/cpus/x86_64_v2/MulIX86.java | 9 +- .../simple/node/cpus/x86_64_v2/MulX86.java | 5 +- .../simple/node/cpus/x86_64_v2/NewX86.java | 27 +- .../simple/node/cpus/x86_64_v2/OrIX86.java | 5 +- .../simple/node/cpus/x86_64_v2/OrX86.java | 35 ++ .../simple/node/cpus/x86_64_v2/ParmX86.java | 9 +- .../simple/node/cpus/x86_64_v2/ProjX86.java | 12 +- .../simple/node/cpus/x86_64_v2/RetX86.java | 26 +- .../simple/node/cpus/x86_64_v2/SarIX86.java | 39 ++ .../simple/node/cpus/x86_64_v2/SarX86.java | 17 +- .../simple/node/cpus/x86_64_v2/SetX86.java | 4 +- .../simple/node/cpus/x86_64_v2/ShlIX86.java | 2 + .../simple/node/cpus/x86_64_v2/ShlX86.java | 39 ++ .../simple/node/cpus/x86_64_v2/ShrIX86.java | 2 + .../simple/node/cpus/x86_64_v2/ShrX86.java | 40 ++ .../simple/node/cpus/x86_64_v2/SplitX86.java | 21 + .../simple/node/cpus/x86_64_v2/StoreX86.java | 12 +- .../simple/node/cpus/x86_64_v2/SubFX86.java | 2 + .../simple/node/cpus/x86_64_v2/SubX86.java | 2 + .../simple/node/cpus/x86_64_v2/TFPX86.java | 13 +- .../simple/node/cpus/x86_64_v2/XorIX86.java | 5 +- .../simple/node/cpus/x86_64_v2/x86_64_v2.java | 263 +++++++---- .../com/seaofnodes/simple/print/ASMPrinter.java | 163 +++++++ .../seaofnodes/simple/print/GraphVisualizer.java | 287 ++++++++++++ .../com/seaofnodes/simple/print/IRPrinter.java | 328 +++++++++++++ .../java/com/seaofnodes/simple/print/JSViewer.java | 405 ++++++++++++++++ .../seaofnodes/simple/print/SimpleWebSocket.java | 149 ++++++ .../com/seaofnodes/simple/type/TypeFunPtr.java | 4 +- .../com/seaofnodes/simple/type/TypeStruct.java | 1 + .../java/com/seaofnodes/simple/type/TypeTuple.java | 2 + .../java/com/seaofnodes/simple/BrainFuckTest.java | 14 +- .../java/com/seaofnodes/simple/Chapter01Test.java | 1 + .../java/com/seaofnodes/simple/Chapter02Test.java | 1 + .../java/com/seaofnodes/simple/Chapter03Test.java | 2 +- .../java/com/seaofnodes/simple/Chapter04Test.java | 1 + .../java/com/seaofnodes/simple/Chapter05Test.java | 1 + .../java/com/seaofnodes/simple/Chapter06Test.java | 1 + .../java/com/seaofnodes/simple/Chapter07Test.java | 1 + .../java/com/seaofnodes/simple/Chapter08Test.java | 1 + .../java/com/seaofnodes/simple/Chapter09Test.java | 2 +- .../java/com/seaofnodes/simple/Chapter10Test.java | 1 + .../java/com/seaofnodes/simple/Chapter11Test.java | 3 +- .../java/com/seaofnodes/simple/Chapter12Test.java | 5 +- .../java/com/seaofnodes/simple/Chapter13Test.java | 14 + .../java/com/seaofnodes/simple/Chapter14Test.java | 4 +- .../java/com/seaofnodes/simple/Chapter15Test.java | 13 +- .../java/com/seaofnodes/simple/Chapter16Test.java | 1 + .../java/com/seaofnodes/simple/Chapter17Test.java | 7 +- .../java/com/seaofnodes/simple/Chapter18Test.java | 13 +- .../java/com/seaofnodes/simple/Chapter19Test.java | 88 ++-- .../java/com/seaofnodes/simple/Chapter20Test.java | 185 +++++++- .../src/test/java/com/seaofnodes/simple/Eval2.java | 4 +- .../src/test/java/com/seaofnodes/simple/Main.java | 2 + .../java/com/seaofnodes/simple/MergeSortTest.java | 12 +- .../java/com/seaofnodes/simple/SchedulerTest.java | 1 + .../java/com/seaofnodes/simple/fuzzer/Fuzzer.java | 2 +- .../com/seaofnodes/simple/fuzzer/FuzzerUtils.java | 2 +- 233 files changed, 9141 insertions(+), 2501 deletions(-) create mode 100644 chapter20/docs/ifg_trim.pdf create mode 100644 chapter20/docs/pardoe.docx delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/ASMPrinter.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/CodeGen.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/GlobalCodeMotion.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/GraphVisualizer.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/IRPrinter.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/JSViewer.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/ListScheduler.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/Machine.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/RegMask.java delete mode 100644 chapter20/src/main/java/com/seaofnodes/simple/SimpleWebSocket.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/BuildLRG.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/CodeGen.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/GlobalCodeMotion.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/IFG.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/LRG.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/ListScheduler.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/Machine.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/RegAlloc.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/codegen/RegMask.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/CalleeSaveNode.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/SplitNode.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddFARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/AddIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/AndIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/AsrIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/BranchARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallEndARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/CallRRARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpFARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/CmpMemARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/DivFARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/FloatARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/FunARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/I2F8ARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/IntARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/LoadARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/LslIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/LsrIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/MemOpARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulFARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/MulIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/NewARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/OrIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/ParmARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/ProjARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/RetARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/SetARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/SplitARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/StoreARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/SubFARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/TFPARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/XorIARM.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/arm.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/arm/i2f8.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddFRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/BranchRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallEndRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CallRRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CastRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/DivFRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/DivRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FltRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/FunRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/I2F8RISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/ImmRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LoadRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MemOpRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulFRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/NewRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/ParmRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/ProjRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetFRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SubFRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SubRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorIRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorRISC.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/AndX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/CallEndX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/CastX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/CmpFX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/OrX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/SarIX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/ShlX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/ShrX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/node/cpus/x86_64_v2/SplitX86.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/print/ASMPrinter.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/print/GraphVisualizer.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/print/IRPrinter.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/print/JSViewer.java create mode 100644 chapter20/src/main/java/com/seaofnodes/simple/print/SimpleWebSocket.java (limited to 'chapter20') diff --git a/chapter20/Makefile b/chapter20/Makefile index 4c1e1f49..f96cfea3 100644 --- a/chapter20/Makefile +++ b/chapter20/Makefile @@ -53,7 +53,7 @@ endif default: $(default_targets) # Compile just the out-of-date files -$(main_classes): build/classes/main/%class: $(SRC)/%java +$(main_classes): $(CLZDIR)/main/%class: $(SRC)/%java @echo "compiling " $@ " because " $? @[ -d $(CLZDIR)/main ] || mkdir -p $(CLZDIR)/main @javac $(JAVAC_ARGS) -cp "$(CLZDIR)/main$(SEP)$(jars)" -sourcepath $(SRC) -d $(CLZDIR)/main $(main_javas) @@ -64,7 +64,7 @@ $(test_classes): $(CLZDIR)/test/%class: $(TST)/%java $(main_classes) @javac $(JAVAC_ARGS) -cp "$(CLZDIR)/test$(SEP)$(CLZDIR)/main$(SEP)$(jars)" -sourcepath $(TST) -d $(CLZDIR)/test $(test_javas) # Base launch line for JVM tests -JVM=nice java -ea -cp "build/classes/main${SEP}${jars}${SEP}$(CLZDIR)/test" +JVM=nice java -ea -cp "$(CLZDIR)/main${SEP}${jars}${SEP}$(CLZDIR)/test" tests: $(default_targets) @echo "testing " $(test_cp) @@ -75,6 +75,14 @@ fuzzer: $(default_targets) @echo "fuzzing " $(test_cp) @$(JVM) org.junit.runner.JUnitCore com.seaofnodes.simple.FuzzerWrap +# Build a Simple jar +release: build/release/simple.jar + +# Build a Simple jar +build/release/simple.jar: $(main_classes) $(test_classes) + @echo "jarring " $@ " because " $? + @[ -d $(dir $@) ] || mkdir -p $(dir $@) + @jar cf build/release/simple.jar -C $(CLZDIR)/main . -C $(CLZDIR)/test . -C $(SRC)/$(SIMPLE) . -C $(TST)/$(SIMPLE) . # Launch viewer view: $(main_classes) diff --git a/chapter20/README.md b/chapter20/README.md index d3d0fddd..ae2b9df0 100644 --- a/chapter20/README.md +++ b/chapter20/README.md @@ -1,9 +1,433 @@ # Chapter 20: Graph Coloring Register Allocation -This is a Briggs-Chaitan-Click allocator, and is very similar to the one used +## Some Reading Material + +This is a Briggs-Chaitin-Click allocator, and is very similar to the one used in HotSpot's C2 allocator for the past 25 years with great success. +Wikipedia has a nice overview of register allocation in general: https://en.wikipedia.org/wiki/Register_allocation + +Chaitin's original: https://en.wikipedia.org/wiki/Register_allocation#CITEREFChaitin1982 + +Briggs additions: https://dl.acm.org/doi/10.1145/177492.177575 + +There are several other useful link that can be found by searching for Briggs +or Chaitin in combination. Basically there was a spate of register allocation +improvements in this era that made it into many high-end mainstream compilers. + +I've included a very old unpublished paper on speeding up graph coloring +allocators: [Interference Graph Triming](docs/ifg_trim.pdf). + You can also read [this chapter](https://github.com/SeaOfNodes/Simple/tree/linear-chapter20) in a linear Git revision history on the [linear](https://github.com/SeaOfNodes/Simple/tree/linear) branch and [compare](https://github.com/SeaOfNodes/Simple/compare/linear-chapter19...linear-chapter20) it to the previous chapter. -## Registers + +## The Basic Theory + +The reading material includes several explainations of the basic concepts, but +at the risk of being redundant I'll present a short version again here. + +I assume you (the reader) know *why* register allocation is required: machine +registers are a high value finite resource, and as with all finite resources +they need to be allocated well. + +Graph Coloring is one such allocation method; machine registers are treated as +colors; a *live range interference graph* is built, with each *live range* +requiring its own register/color. Coloring the graph ensures every live range +gets a unique register, specificially when it overlaps or *interferes* with +another live range. + +A successful coloring ends the allocation and after some bookkeeping the +program is ready for e.g. code emission. A failed coloring requires spilling +or splitting conflicting live ranges; in this allocator we will be doing live +range *splitting*. Splitting live ranges makes them more colorable; they +become shorter with fewer interfering other live ranges. Generally large +functions might require a few rounds of splitting before becoming colorable. +Since the problem is NP-complete there are no guarantees here, the final +allocation quality becomes heavily dependent on splitting and coloring +heuristics. + +Hence, much of the "high theory" will be used to drive the core coloring +algorithm, but much of the "actual success" will depend on a large collection +of heuristics. + +### Coloring Rounds + +Coloring proceeds in rounds until we get a coloring: + +- Build the Live Ranges; live ranges require the same register for all + instructions in the live range. Phi functions will force unrelated def/use + edges to become part of the same live range and this can drive large + interconnected live ranges with a lot of conflicts. Some hardware ops + require the same register for both inputs and outputs (X86 is notorious here) + which also makes fewer larger live ranges. We'll be using the disjoint + Union-Find algorithm to rapidly build up live ranges in one forward pass over + the program. + +- Build the Inteference Graph: every live range which is alive at the same time + as any other, now *interferes* or conflicts. This is built using a LIVE-ness + pass, which is a backwards pass over the CFG, and can require more than one + pass according to loop nesting depth. The data structure here is generally a + 2-D bitset, triangulated to cut its size in half. As part of LIVE, we'll + also have a set of reaching defs per-block. + +- Color the interference graph. Nodes (live ranges) in the graph which are + strictly low degree (more available registers than neighbors) will guaranteed + get a color. These can be removed from the graph - since they will + guaranteed get a register (color) because they have so few conflicting + neighbors. Removing these trivial nodes makes more nodes go trivial, and + this process repeats until either we run out (and are guaranteed a coloring) + or we find a high-degree clique: a set of mutually interfering live ranges + where none of them are guaranteed a color. In this case we pull an "at risk" + live range out; this one might not color. Once the graph is emptied, we + reverse and re-insert the live ranges, coloring as we go. All the trivial + live ranges will color; the at-risk ones may or may not. + +- If every live range gets a color, then Register Allocation is done. If not, + we enter a round of splitting. Live ranges which did not color are now split + via a series of heuristics into lots of small live ranges. Splitting has a + tension: too much and you got a lot of spills (and a generally poor + allocation). Too little, and you remain uncolorable - and do not make + progress towards an allocation. Once we're done splitting, we start a new + round of coloring (Building the Live Ranges, then the Interference Graph, + then Coloring). + + +## Registers and Register Masks + +Registers are the thing that Register Allocation is all about! They are +represented as a small dense integer, starting up from 0, and the numbering +generally follows from the hardware encodings. So for an X86_64, RAX will be +register 0, RCX register 1 and so on up to the 16 GPRs. The XMM registers at +16 and go up to 32. Register numbers must be unique; this is how the register +allocator tracks them. + +#### Why a RegMask class and not a simple `long`? + +A collection of registers live in a Register Mask. For smaller and simpler +machines it suffices to make such masks an i64 or i128 (64 or 128 bit +integers), and this presentation is by far the better way to go... if all +register allocations can fit in this bit limitation. The allocator will need +bits for stack-based parameters and for splits which cannot get a register. +For a 32-register machine like the X86, add 1 for flags - gives 33 registers. +Using a Java `long` has 64 bits, leaving 31 for spills and stack passing. This +is adequate for nearly all allocations; only the largest allocations will run +this out. However, if we move to a chip with 64 registers we'll immediately +run out, and need at least a 128 bit mask. Since you cannot *return* a 128 +bit value directly in Java, Simple will pick up a `RegMask` class object. + +#### Stack Slots + +One of the Click extensions is this notion of treating "stack slots" are Just +Another Register. They get colored like other registers, which in turn leads +to very efficient use of the stack; C2 is known for having very small stack +frames. Another benefit is callee save registers will get split preferentially +(they have very long lifetime and only one def on entry and one use on +exit)... which the splits then end up coloring to the stack, building the call +prolog and epilog naturally. This allocator will not otherwise dedicate any +effort to stack frame management; it will "fall out in the wash". + +Many of the register masks are immutable; e.g. allowed registers for particular +opcodes, or describing registers for calling conventions. Other masks +represent mutable bitsets with the allocator routinely masking off bits when +accumulating a set of constraints. To help keep these uses apart, the +`RegMask` class includes mutable and immutable variants. + + +### Callee/Caller Save Registers + +In this allocator, callee- and caller-save registers get almost no special +treatment and no special prolog nor epilog is built to save and restore them. +At the start of the allocator, SoN graph edges are added between each `Return` +and a `CalleeSave` from each `Fun`. These edges are given register masks +pinning them to the callee-save set as defined by the normal ABI. + +Callee-save live ranges thus have a single def (a `CalleeSave` at function +start) and a single use (the `Return`), are cheap to spill and free a register +over a large area - they make ideal spill candidates. When the allocator needs +to spill something to get some more registers, these will be the first to +spill. A prolog and epilog will get built as a consequence of the normal live +range splitting process. + +`Calls` kill the caller-save registers (just the inverted callee-save mask), +and this is computed during the normal interference graph building process just +like any other operation that kills registers. Killing a bunch of registers at +a call typically removes all the free registers from whatever is currently +alive - and will thus force spilling... which will quickly end up spilling +callee-save registers as ideal candidates. + + +## Live Ranges + +A live range is a set of nodes and edges which must get the same register. +Live ranges form an interconnected web with almost no limits on their shape. +Live ranges also gather the set of register constraints from all their parts. + +Live ranges are held in `LRG` class instances. Most of the fields in this +class are for spill heuristics, but there are a few key ones that define what a +LRG is. `RegAlloc` has several functions dealing with LRGs, including a lookup +table from Nodes i.e., a mapping from `Node` to `LRG` (which is very similar to +having a dedicated LRG field in each Node... except that LRGs are only used +during RegAlloc and the field would be dead weight otherwise). + +LRGs have a unique dense integer `_lrg` number which names the LRG. New `_lrg` +numbers come from the `RegAlloc._lrg_num` counter. LRGs can be unioned +together - +[this is the Union-Find algorithm](https://en.wikipedia.org/wiki/Disjoint-set_data_structure) +- and when this happens the lower numbered `_lrg` wins. Unioning only happens +during `BuildLRG` and happens because either a `Phi` is forcing all its inputs +and outputs into the same register, or because of a 2-address instruction. +LRGs have matching `union` and `find` calls, and a set `_leader` field. + +Post-allocation the `LRG._reg` field holds the chosen register. During +allocation the `LRG._mask` field holds the set of available registers, +typically all the defaults, minus various conflicts. + +The `LRG._adj` holds a list of adjacent neighbors as part of the larger +Interference Graph, and is only used during the Coloring phase. +[See more about graphs here.](https://en.wikipedia.org/wiki/Graph_(abstract_data_type)) +This is a "adjacency list" form of a Graph description, and is built from the +IFG's 2-D collection of bits (itself a 1-D list of `BitSet`s). Graph coloring +register allocation is one of the few places where changing the layout of a +data structure mid-algorithm pays out. + +The rest of the fields are dedicated to various spilling heuristics: + +- `_machDef` `_machUse` `_uidx` - A sample def and use. +- `_splitDef` `_splitUse` - Sample splits involved with this LRG; biased + coloring attempts to align register choices to remove these. +- `_selfConflicts` - A partial set of *self-conflicting* nodes. These are + detected during the Interference Graph build phase, and require aggressive + splitting. +- `_1regDefCnt` `_1regUseCnt` - Count of defs and uses which are pinned to a + single register. These typically require a hard-split just before (use) or + after (def) to free up the register choices. +- `_killed` - LRG lost all registers due to an op killing its available + registers; commonly happens to LRGs which span a `Call` and generally + requires splitting some callee-save live range (spilling a callee-save + register) and move the LRG into the now available register. + + +## Live Ranges and Conflicts + +If the live range `_mask` field goes empty, you might have a *hard conflict* or +have gotten *killed*. Live ranges can self-interfere, making a +*self-conflict*. During coloring you might discover an uncolorable clique of +interfering live ranges, leading to a *capacity spill*. This leads to a set of +levels of conflicts within a live range (and thus a different heuristics for +handling them). + +### Hard-Conflicts + +A live range can have a *hard confict*: conflicting register requirements, +leading to no valid register choices. The obvious case is an incoming +parameter fixed in e.g. `rdx` but also required as an exit value in `rax`. You +can't pick both registers at once, so a split is required. During the build +live ranges phase, every register constraint from every def and use are AND'd +together; the `RegMask` might lose all valid registers, or remain with just a +handful of register choices. + +Hard-conflicts are usually found while build live ranges, and will trigger a +round of splitting before building the interference graph or coloring. They +can also be found during interference graph building, generally caused by a +1-register kill. + +### Avoiding interferences + +Once of the Click extensions to the Briggs-Chaitin allocator is to take +advantage of register constraints to lower the interference graph degree (which +otherwise becomes an O(n^2) edge collection). If a live range LR1 is reduced +to a single register (such as a call argument requiring `rdx`) and would +otherwise conflict with another live range LR2 which has more choices - we +remove `rdx` from the LR2's choices. Without having `rdx`, LR1 and LR2 have no +registers in common - and hence do not conflict. We just don't add the +interference graph edge between them. Call argument restrictions are very +common and this kind of edge-removal can dramatically shrink the O(n^2) edge +collection - and hence speedup allocation by a large constant factor. + +### Self-Conflicts + +A live-range can *self-conflict* be alive twice with 2 different values but +require the same register. This live range *must* split and thus picks up a +copy from the split. This happens with loop-carried dependencies as seen in +e.g. a simple `fib` program: + +```java + int x=1, y=1; + while( true ) { + tmp = x + y; + y = x; + x = tmp; + }; + +``` + +In SoN SSA form: +```java + int x0 = 1, y0 = 1; + while( true ) { + x1 = phi(x0,x2); + y1 = phi(y0,x1); + x2 = x1 + y1; + } +``` + +The variables `x0,x1,x2,y0,y1` all form part of the same live range, since they +are all joined by `Phis`. However, `x1` and `y1` hold different values from +different iterations of `fib`. The SSA form does not have a copy, but the +register-allocated form - just like the original code - DOES require a copy. + +Self-conflicts are found during building the interference graph, and will +trigger a round of splits before attempting the coloring phase. + + +## Coloring Heuristics + +Both register coloring and register splitting are full of heuristics, and the +quality of these heuristics goes a long way to deciding the quality of the +final allocation. Graph coloring is NP-complete; there is no efficient +algorithm for coloring and many programs are simply not colorable without +splitting in any case. + + +### Biased Coloring + +Biased coloring is a heuristic that attempts to "pick a better color" or "bias +the color choice", such that a Split is removed. A Split splits one live range +into two; sometimes some are inserted that are not required (i.e., over- +splitting has already happened). If one side (live range) of a split is +already colored and we can color the other side (live range) the same color - +then this split can be removed. If neither side is colored, but one or the +other side is recursively connected to a colored live range, we can still bias +the color in the hopes that a chain of splits will all get the same color and +thus all get removed. + +When the coloring process is reversing, and colors are being picked for live +ranges, we often have many register choices. A first choice is made +arbitrarily (lowest numbered register), and then we go looking for a better +color. Biased coloring inspects first a sample def (if there is only one, then +the One Def is inspected), and then a sample use. Inspection looks to see if +"the other side" of a split is already colored; if so, and that color is +available it is choosen. If there is a split, but it is not colored - we +recursively repeat the process on that split's other side. This is also done +for the other input of two-address ops and one of a Phi node inputs. + +In all cases, the goal is to pick a valid available color - that might also +eventually be pick-able for this Split's other side - and lead to this split +having the same color for both sides, and then being removed. + + +### Pick Risky + +Here we are forced to pick one of several *live ranges* that form a large +clique: they have too many mutual neighbors so that no one of them is +guaranteed a color. There is a conflicting tension here: + +Picking a live range with a large "area" (i.e. covering much of the program), +and low "cost" to spill (i.e. fewer defs and uses, and outside of loops) will +give a large win. A register will become free over a large part of the program +and allow coloring to success elsewhere. The normal ABI callee-save registers +are ideal in this case, defined on entry and used only on exit they cover the +entire program. Also, spilling means only a single split on entry and another +at exit. Spilling such live ranges basically builds a classic function +prolog/epilog sequence. Here though, the allocator is allowed to e.g. spill +outside a fast-path exit. + +``` + // No registers saved if the initial RDI is null + test rdi + jne BIG_AND_SLOW + xor rax,rax + ret // Fast path exit: null argument means null result +BIG_AND_SLOW: + add rsp,#12 + mov [rsp+0],rbx // begin spilling callee-save registers + mov [rsp+4],r12 // + // lots of code needing callee-save registers +``` + +The other side of the tension is to pick live ranges that are likely to color +more by chance. If a live range is "very nearly colorable" - say only one more +neighbor than available registers/colors then by chance (and Biased Coloring) +some neighbors might use the same color... freeing up a color and allowing this +risky live range to color after all. + + +## Splitting + +Here we failed to get a coloring - and need to split. Some specific live +ranges did not color and we will need to decide how to split. Again there are +tensions here: too much splitting leads to a bad allocation, to little leads to +no-progress bugs (manifested as too many rounds of splitting past some +arbitrary cutoff). + +We start by looking at each spilling live range in turn, and deciding +on a splitting strategy. + + +### Split Self Conflict + +Self-conflict live ranges are discovered during the "Build the Interference +Graph" stage. If this happens we don't attempt a coloring (its nonsensical +with self conflicts), but go straight to splitting. During the IFG building we +gathered a subset of the conflicting definitions for this live range. Now +we visit all those definition points and insert spills: + +- Before slot #1 on a Phi (which breaks loop-entry Phis from the loop-body) and + also after the Phi. +- Before a two-address instruction, breaking the live range before the op from + afterwards. +- Before any use that extends a live range. + +This set of splits is fairly aggressive... but test cases requiring a split in +each of the listed locations are including in Chapter 20's test cases. We +cannot even attempt a color while we have self conflicts, so its important to +break up these live ranges quickly. This tends to over-split and the allocator +leans on Biased Coloring to remove some of the extras. + + +### Split Hard Conflict + +Hard conflicts are discovered during the "Build the Live Ranges" pass for +direct def/use conflicts (e.g. defined in `rdi` and used in `rax`). They also +can be discovered during the "Build the Interference Graph" pass (e.g. incoming +argument in `rdi` used later in the program and killed by a `Call`). + +For simple hard-conflicts, we have the exact def and use kept in the Live Range +itself. We split once after the def and once before the use (and only on sides +with restricted registers). + +For more complex cases we use the capacity spilling/loop-nest technique. + + +### Split By Loop Nest + +Here we typically see capacity spills: we just need more registers. This +easily happens when a `Call` crushes all the temporary registers and we need to +carry some values past the call - but it can also happen any time we have a +larger function with lots of things going on at once. + +The heuristic here is to split *around* loops, attempting to keep some free +registers available so the hot loop body does not spill. Live ranges are split +into successively deeper loop nests in progressive rounds of splitting, and in +the final case will split once after each def and before each use, even in the +innermost loop. + +The heurstic starts by discovering the min and max loop depth for all defs and +uses. If these vary, we will split *around* the outermost loop, putting in +splits at the loop border and keeping an inner untouched live range that has no +constraints from outside. If this fails to color, on the next round of +splitting the outermost loop will have moved in one layer, and we will be +splitting around the next inner loop nest. This process repeats until we end +up splitting in the inner-most loops. + + +## Post Allocation + +After a successful coloring, we want to pull out any same-same register splits. +A quick pass over the splits and after checking registers, we pull out the +useless splits (and track the rest for "scoring" our allocation). We'll also +bypass some split-after-splits, which can remove some redundant copying. + +The registers remain available in the `RegAlloc` object via `alloc.regnum( Node n )` +and will be used by a following instruction encoding pass. \ No newline at end of file diff --git a/chapter20/docs/ifg_trim.pdf b/chapter20/docs/ifg_trim.pdf new file mode 100644 index 00000000..d952fd4f Binary files /dev/null and b/chapter20/docs/ifg_trim.pdf differ diff --git a/chapter20/docs/pardoe.docx b/chapter20/docs/pardoe.docx new file mode 100644 index 00000000..24fde921 Binary files /dev/null and b/chapter20/docs/pardoe.docx differ diff --git a/chapter20/src/main/java/com/seaofnodes/simple/ASMPrinter.java b/chapter20/src/main/java/com/seaofnodes/simple/ASMPrinter.java deleted file mode 100644 index 5cc13210..00000000 --- a/chapter20/src/main/java/com/seaofnodes/simple/ASMPrinter.java +++ /dev/null @@ -1,140 +0,0 @@ -package com.seaofnodes.simple; - -import com.seaofnodes.simple.node.*; -import com.seaofnodes.simple.SB; -import com.seaofnodes.simple.type.TypeFunPtr; -import com.seaofnodes.simple.type.TypeMem; -import com.seaofnodes.simple.type.TypeRPC; - -public abstract class ASMPrinter { - - public static SB print(SB sb, CodeGen code) { - if( code._cfg==null ) - return sb.p("Need _cfg set, run after GCM"); - - // instruction address - int iadr = 0; - for( int i=0; i