From 586c8f65f2d0c0e1f73aadd0aa8d850aa653bddd Mon Sep 17 00:00:00 2001 From: Cliff Click Date: Mon, 28 Sep 2026 13:30:22 -0700 Subject: Support extern C ver direct updates FIx minor RISC encodings. --- .../main/java/com/seaofnodes/simple/node/cpus/riscv/TMPRISC.java | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'chapter24/src/main/java/com/seaofnodes') diff --git a/chapter24/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TMPRISC.java b/chapter24/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TMPRISC.java index 44e73d1d..94f0da0e 100644 --- a/chapter24/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TMPRISC.java +++ b/chapter24/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TMPRISC.java @@ -28,9 +28,9 @@ public class TMPRISC extends ConstantNode implements MachNode, RIPRelSize { // Delta is from opcode start @Override public void patch( Encoding enc, int opStart, int opLen, int delta ) { short dst = enc.reg(this); - // AUIPC dst,#hi20_constant_pool - enc.patch4(opStart , riscv.u_type(riscv.OP_AUIPC, dst, delta>>12)); - // Load dst,[dst+#low12_constant_pool] + // Round the high part because ADDI's low 12 bits are signed. + enc.patch4(opStart , riscv.u_type(riscv.OP_AUIPC, dst, (delta+0x800)>>12)); + // ADDI dst,dst,#low12_constant_pool enc.patch4(opStart+4, riscv.i_type(riscv.OP_IMM, dst, 0, dst, delta & 0xFFF)); } -- cgit v1.2.3