From 87a75c83b75480e65147a4d425fddd14a05df4d9 Mon Sep 17 00:00:00 2001 From: Cliff Click Date: Wed, 7 Oct 2026 21:31:18 -0700 Subject: More test case vs RA cleanup Missing a few risc/arm encodings. Make private many tests, so they don't escape and the escaped fcn inflate x86 spill numbers --- .../java/com/seaofnodes/simple/Chapter24Test.java | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'chapter24/src/test/java/com/seaofnodes') diff --git a/chapter24/src/test/java/com/seaofnodes/simple/Chapter24Test.java b/chapter24/src/test/java/com/seaofnodes/simple/Chapter24Test.java index bb89aa16..9a657855 100644 --- a/chapter24/src/test/java/com/seaofnodes/simple/Chapter24Test.java +++ b/chapter24/src/test/java/com/seaofnodes/simple/Chapter24Test.java @@ -585,17 +585,21 @@ return 0 < arg < arg+1 < 4; """; TestC.run(src, "stacked_r_13x", null, stack12,0); - // Evaluate on RISC5 emulator + // Compile once per target, then check false, true and negative inputs. EvalRisc5 R5 = TestRisc5.build("stacked_r_13", src2, 1, 0, false); - int trap = R5.step(100); - assertEquals(0,trap); - assertEquals(1,R5.regs[riscv.A0]); - - // Evaluate on ARM emulator + for( int arg : new int[]{-1,0,1} ) { + R5._pc = 0; + R5.regs[riscv.A0] = arg; + assertEquals(0,R5.step(100)); + assertEquals(arg==0 ? 1 : 0,R5.regs[riscv.A0]); + } EvalArm64 arm = TestArm64.build("stacked_r_13", src2, 1, 0, false); - trap = arm.step(100); - assertEquals(0,trap); - assertEquals(1,arm.regs[0]); + for( int arg : new int[]{-1,0,1} ) { + arm._pc = 0; + arm.regs[0] = arg; + assertEquals(0,arm.step(100)); + assertEquals(arg==0 ? 1 : 0,arm.regs[0]); + } } @Test -- cgit v1.2.3