From 300d2a9c3672acacc8bdd8d5370a424651a00571 Mon Sep 17 00:00:00 2001 From: Cliff Click Date: Sun, 18 Oct 2026 22:09:58 -0700 Subject: Cleanup & backport The phase rework, made new phases explicit and add them to the CodeGen driver. Fix the flag-spilling on X86 and ARM. Fix the GCM conservative anti-deps and backport. --- .../java/com/seaofnodes/isa/eval/EvalArm64.java | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'isa/src/test-support/java') diff --git a/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java b/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java index 1ff77f59..d4a54719 100644 --- a/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java +++ b/isa/src/test-support/java/com/seaofnodes/isa/eval/EvalArm64.java @@ -597,6 +597,22 @@ public class EvalArm64 { break; } + case 0xD5: { + if( (ir & ~31)==0xD53B4200 ) { // MRS Xt,NZCV + rval = (N ? 1L<<31 : 0) | (Z ? 1L<<30 : 0) | + (C ? 1L<<29 : 0) | (V ? 1L<<28 : 0); + if( rdid==31 ) rdid=-1; // XZR, not SP. + } else if( (ir & ~31)==0xD51B4200 ) { // MSR NZCV,Xt + long value = rdid==31 ? 0 : regs[rdid]; + N = (value & (1L<<31))!=0; + Z = (value & (1L<<30))!=0; + C = (value & (1L<<29))!=0; + V = (value & (1L<<28))!=0; + rdid=-1; + } else throw new UnsupportedOperationException("Unknown system instruction"); + break; + } + case 0xD6: { int op = ir & 0xFFFFFC1F; int rn = (ir >>> 5) & 31; -- cgit v1.2.3