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-rw-r--r--CHANGELOG.md13
-rw-r--r--LICENSES.txt2
-rw-r--r--docs/latest/draft-tasd-spec.html236
-rw-r--r--docs/latest/draft-tasd-spec.txt113
-rw-r--r--docs/tasd-spec-0001/draft-tasd-spec-0001.html236
-rw-r--r--docs/tasd-spec-0001/draft-tasd-spec-0001.txt113
-rw-r--r--src/docs/draft-tasd-spec-0001.xml13
7 files changed, 640 insertions, 86 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 383f729..812e876 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -3,6 +3,18 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), although currently without version numbers added.
+
+## 2023-07-06
+### Added
+- rasteri to `LICENSES.txt`, spec contributors list, and spec LICENSE
+
+### Removed
+- VG Interactive organization Vi Grey
+
+### Fixed
+- \<bcp14\> tag around MUST instead of \<strong\> tag in spec
+
+
## 2023-07-06
### Added
- SNES Super Multitap input format to spec
@@ -12,6 +24,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
- Updated copyright year in `LICENSES.txt` and in spec
- Reordered Genesis 3-button and 6-button controller formats
+
## 2023-07-03
### Added
- SNES\_LATCH\_TRAIN to spec
diff --git a/LICENSES.txt b/LICENSES.txt
index 1530cc3..85fc037 100644
--- a/LICENSES.txt
+++ b/LICENSES.txt
@@ -1,5 +1,5 @@
TASD File Format Specification Version 1
- Copyright (c) 2021-2023, Vi Grey and Bigbass
+ Copyright (c) 2021-2023, Vi Grey, Bigbass, and rasteri
All rights reserved.
diff --git a/docs/latest/draft-tasd-spec.html b/docs/latest/draft-tasd-spec.html
index 60a7a65..5daf4c9 100644
--- a/docs/latest/draft-tasd-spec.html
+++ b/docs/latest/draft-tasd-spec.html
@@ -7,6 +7,7 @@
<title>TASD File Format Specification Version 1</title>
<meta content="Vi Grey" name="author">
<meta content="Bigbass" name="author">
+<meta content="rasteri" name="author">
<meta content='
The TASD file format is used for storing "Tool Assisted Speedrun" or "Tool Assisted Superplay" (TAS) data for TAS replay devices to replay on physical video game console hardware. The format is defined to be expandable for future needs. The format is also defined to be parsable by programs that do not understand portions of the format, whether that is due to incomplete support of the format specification or due to new features being added to later versions of the specification at a later date.
This document defines the file format specification for TASD files.
@@ -1206,7 +1207,7 @@ li > p:last-of-type:only-child {
<td class="right">July 2023</td>
</tr></thead>
<tfoot><tr>
-<td class="left">Grey &amp; Bigbass</td>
+<td class="left">Grey, et al.</td>
<td class="center">Informational</td>
<td class="right">[Page]</td>
</tr></tfoot>
@@ -1218,17 +1219,19 @@ li > p:last-of-type:only-child {
<dd class="workgroup">Independent TAS Console Replay Research Group</dd>
<dt class="label-published">Published:</dt>
<dd class="published">
-<time datetime="2023-07-03" class="published">3 July 2023</time>
+<time datetime="2023-07-06" class="published">6 July 2023</time>
</dd>
<dt class="label-authors">Authors:</dt>
<dd class="authors">
<div class="author">
<div class="author-name">V. Grey</div>
-<div class="org">VG Interactive</div>
</div>
<div class="author">
<div class="author-name">Bigbass</div>
</div>
+<div class="author">
+ <div class="author-name">rasteri</div>
+</div>
</dd>
</dl>
</div>
@@ -1494,6 +1497,9 @@ li > p:last-of-type:only-child {
<li class="compact toc ulBare ulEmpty" id="section-toc.1-1.4.2.2.2.2">
<p id="section-toc.1-1.4.2.2.2.2.1"><a href="#section-4.2.2" class="auto internal xref">4.2.2</a>.  <a href="#name-snes-mouse" class="internal xref">SNES Mouse</a></p>
</li>
+ <li class="compact toc ulBare ulEmpty" id="section-toc.1-1.4.2.2.2.3">
+ <p id="section-toc.1-1.4.2.2.2.3.1"><a href="#section-4.2.3" class="auto internal xref">4.2.3</a>.  <a href="#name-snes-super-multitap" class="internal xref">SNES Super Multitap</a></p>
+</li>
</ul>
</li>
<li class="compact toc ulBare ulEmpty" id="section-toc.1-1.4.2.3">
@@ -3922,6 +3928,188 @@ li > p:last-of-type:only-child {
<dd class="break"></dd>
</dl>
</section>
+<section id="section-4.2.3">
+ <h4 id="name-snes-super-multitap">
+<a href="#section-4.2.3" class="section-number selfRef">4.2.3. </a><a href="#name-snes-super-multitap" class="section-name selfRef">SNES Super Multitap</a>
+ </h4>
+<p id="section-4.2.3-1">Single Input Length: 5 Octets<a href="#section-4.2.3-1" class="pilcrow">¶</a></p>
+<p id="section-4.2.3-2"><strong>Octet 0</strong> :<a href="#section-4.2.3-2" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-3">
+ <dt id="section-4.2.3-3.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.2">1<a href="#section-4.2.3-3.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.4">1<a href="#section-4.2.3-3.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.6">1<a href="#section-4.2.3-3.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.8">1<a href="#section-4.2.3-3.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.10">1<a href="#section-4.2.3-3.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.12">1<a href="#section-4.2.3-3.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.14">1<a href="#section-4.2.3-3.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.16">I/O Pin State - <strong>1</strong> if Multitap ports <strong>1 and 2</strong> are being polled, <strong>0</strong> if ports <strong>3 and 4</strong> are.<a href="#section-4.2.3-3.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-4"><strong>Octet 1</strong><a href="#section-4.2.3-4" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-5">
+ <dt id="section-4.2.3-5.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.2">Controller N-1 or N-3 /B<a href="#section-4.2.3-5.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.4">Controller N-1 or N-3 /Y<a href="#section-4.2.3-5.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.6">Controller N-1 or N-3 /Select<a href="#section-4.2.3-5.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.8">Controller N-1 or N-3 /Start<a href="#section-4.2.3-5.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.10">Controller N-1 or N-3 /Up<a href="#section-4.2.3-5.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.12">Controller N-1 or N-3 /Down<a href="#section-4.2.3-5.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.14">Controller N-1 or N-3 /Left<a href="#section-4.2.3-5.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.16">Controller N-1 or N-3 /Right<a href="#section-4.2.3-5.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-6"><strong>Octet 2</strong><a href="#section-4.2.3-6" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-7">
+ <dt id="section-4.2.3-7.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.2">Controller N-1 or N-3 /A<a href="#section-4.2.3-7.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.4">Controller N-1 or N-3 /X<a href="#section-4.2.3-7.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.6">Controller N-1 or N-3 /L<a href="#section-4.2.3-7.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.8">Controller N-1 or N-3 /R<a href="#section-4.2.3-7.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.10">1<a href="#section-4.2.3-7.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.12">1<a href="#section-4.2.3-7.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.14">1<a href="#section-4.2.3-7.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.16">1<a href="#section-4.2.3-7.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-8"><strong>Octet 3</strong><a href="#section-4.2.3-8" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-9">
+ <dt id="section-4.2.3-9.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.2">Controller N-2 or N-4 /B<a href="#section-4.2.3-9.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.4">Controller N-2 or N-4 /Y<a href="#section-4.2.3-9.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.6">Controller N-2 or N-4 /Select<a href="#section-4.2.3-9.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.8">Controller N-2 or N-4 /Start<a href="#section-4.2.3-9.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.10">Controller N-2 or N-4 /Up<a href="#section-4.2.3-9.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.12">Controller N-2 or N-4 /Down<a href="#section-4.2.3-9.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.14">Controller N-2 or N-4 /Left<a href="#section-4.2.3-9.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.16">Controller N-2 or N-4 /Right<a href="#section-4.2.3-9.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-10"><strong>Octet 4</strong><a href="#section-4.2.3-10" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-11">
+ <dt id="section-4.2.3-11.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.2">Controller N-2 or N-4 /A<a href="#section-4.2.3-11.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.4">Controller N-2 or N-4 /X<a href="#section-4.2.3-11.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.6">Controller N-2 or N-4 /L<a href="#section-4.2.3-11.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.8">Controller N-2 or N-4 /R<a href="#section-4.2.3-11.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.10">1<a href="#section-4.2.3-11.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.12">1<a href="#section-4.2.3-11.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.14">1<a href="#section-4.2.3-11.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.16">1<a href="#section-4.2.3-11.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-12"><strong>Controller N</strong> is the controller port number on the console that the Multitap is connected to. <strong>Controller N-1...N-4</strong> are the controller ports <strong>1...4</strong> on the Multitap. Two Multitap ports are polled simultaneously by the game - either <strong>1 and 2</strong>, or <strong>3 and 4</strong>. The I/O Pin state in octet 0 <span class="bcp14">MUST</span> be <strong>1</strong> for multitap ports <strong>1 and 2</strong>, or <strong>0</strong> for ports <strong>3 and 4</strong>.<a href="#section-4.2.3-12" class="pilcrow">¶</a></p>
+</section>
</section>
<section id="section-4.3">
<h3 id="name-n64-controller-types">
@@ -4820,35 +5008,35 @@ li > p:last-of-type:only-child {
<p id="section-4.8.1-2"><strong>Octet 0</strong><a href="#section-4.8.1-2" class="pilcrow">¶</a></p>
<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.8.1-3">
<dt id="section-4.8.1-3.1">Bit 7:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.2">/A<a href="#section-4.8.1-3.2" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.2">/Up<a href="#section-4.8.1-3.2" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.3">Bit 6:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.4">/Start<a href="#section-4.8.1-3.4" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.4">/Down<a href="#section-4.8.1-3.4" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.5">Bit 5:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.6">/Up<a href="#section-4.8.1-3.6" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.6">/Left<a href="#section-4.8.1-3.6" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.7">Bit 4:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.8">/Down<a href="#section-4.8.1-3.8" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.8">/Right<a href="#section-4.8.1-3.8" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.9">Bit 3:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.10">/Left<a href="#section-4.8.1-3.10" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.10">/B<a href="#section-4.8.1-3.10" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.11">Bit 2:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.12">/Right<a href="#section-4.8.1-3.12" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.12">/C<a href="#section-4.8.1-3.12" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.13">Bit 1:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.14">/B<a href="#section-4.8.1-3.14" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.14">/A<a href="#section-4.8.1-3.14" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.15">Bit 0:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.16">/C<a href="#section-4.8.1-3.16" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.16">/Start<a href="#section-4.8.1-3.16" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
</dl>
@@ -4861,35 +5049,35 @@ li > p:last-of-type:only-child {
<p id="section-4.8.2-2"><strong>Octet 0</strong><a href="#section-4.8.2-2" class="pilcrow">¶</a></p>
<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.8.2-3">
<dt id="section-4.8.2-3.1">Bit 7:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.2">/A<a href="#section-4.8.2-3.2" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.2">/Up<a href="#section-4.8.2-3.2" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.3">Bit 6:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.4">/Start<a href="#section-4.8.2-3.4" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.4">/Down<a href="#section-4.8.2-3.4" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.5">Bit 5:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.6">/Up<a href="#section-4.8.2-3.6" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.6">/Left<a href="#section-4.8.2-3.6" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.7">Bit 4:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.8">/Down<a href="#section-4.8.2-3.8" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.8">/Right<a href="#section-4.8.2-3.8" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.9">Bit 3:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.10">/Left<a href="#section-4.8.2-3.10" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.10">/B<a href="#section-4.8.2-3.10" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.11">Bit 2:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.12">/Right<a href="#section-4.8.2-3.12" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.12">/C<a href="#section-4.8.2-3.12" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.13">Bit 1:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.14">/B<a href="#section-4.8.2-3.14" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.14">/A<a href="#section-4.8.2-3.14" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.15">Bit 0:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.16">/C<a href="#section-4.8.2-3.16" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.16">/Start<a href="#section-4.8.2-3.16" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
</dl>
@@ -5043,7 +5231,7 @@ li > p:last-of-type:only-child {
<h2 id="name-copyright-notice">
<a href="#name-copyright-notice" class="section-name selfRef">Copyright Notice</a>
</h2>
-<p id="appendix-A-1">Copyright (c) 2021-2022, Vi Grey and Bigbass<a href="#appendix-A-1" class="pilcrow">¶</a></p>
+<p id="appendix-A-1">Copyright (c) 2021-2023, Vi Grey, Bigbass, and rasteri<a href="#appendix-A-1" class="pilcrow">¶</a></p>
<p id="appendix-A-2">All rights reserved.<a href="#appendix-A-2" class="pilcrow">¶</a></p>
<p id="appendix-A-3">Redistribution and use of this documentation in source (XML format) and/or "compiled" forms (TXT, PDF, HTML, etc), with or without modification, are permitted provided that the following conditions are met:<a href="#appendix-A-3" class="pilcrow">¶</a></p>
<ol start="1" type="1" class="normal type-1" id="appendix-A-4">
@@ -5061,7 +5249,6 @@ li > p:last-of-type:only-child {
</h2>
<address class="vcard">
<div dir="auto" class="left"><span class="fn nameRole">Vi Grey</span></div>
-<div dir="auto" class="left"><span class="org">VG Interactive</span></div>
<div class="email">
<span>Email:</span>
<a href="mailto:vi@vigrey.com" class="email">vi@vigrey.com</a>
@@ -5078,6 +5265,13 @@ li > p:last-of-type:only-child {
<a href="https://github.com/bigbass1997" class="url">https://github.com/bigbass1997</a>
</div>
</address>
+<address class="vcard">
+ <div dir="auto" class="left"><span class="fn nameRole">rasteri</span></div>
+<div class="url">
+<span>URI:</span>
+<a href="https://github.com/rasteri" class="url">https://github.com/rasteri</a>
+</div>
+</address>
</section>
</div>
<script>const toc = document.getElementById("toc");
diff --git a/docs/latest/draft-tasd-spec.txt b/docs/latest/draft-tasd-spec.txt
index 655f2c7..cfac083 100644
--- a/docs/latest/draft-tasd-spec.txt
+++ b/docs/latest/draft-tasd-spec.txt
@@ -3,9 +3,11 @@
Independent TAS Console Replay Research Group V. Grey
- VG Interactive
+
Bigbass
- 3 July 2023
+
+ rasteri
+ 6 July 2023
TASD File Format Specification Version 1
@@ -100,6 +102,7 @@ Table of Contents
4.2. SNES Controller Types
4.2.1. SNES Standard Controller
4.2.2. SNES Mouse
+ 4.2.3. SNES Super Multitap
4.3. N64 Controller Types
4.3.1. N64 Standard Controller
4.3.2. N64 Standard Controller with Rumble
@@ -1716,6 +1719,73 @@ Table of Contents
Bits 7-1: /Horizontal displacement since last read
Bit 0: Direction (0: up; 1: down)
+4.2.3. SNES Super Multitap
+
+ Single Input Length: 5 Octets
+
+ *Octet 0* :
+
+ Bit 7: 1
+ Bit 6: 1
+ Bit 5: 1
+ Bit 4: 1
+ Bit 3: 1
+ Bit 2: 1
+ Bit 1: 1
+ Bit 0: I/O Pin State - *1* if Multitap ports *1 and 2* are being
+ polled, *0* if ports *3 and 4* are.
+
+ *Octet 1*
+
+ Bit 7: Controller N-1 or N-3 /B
+ Bit 6: Controller N-1 or N-3 /Y
+ Bit 5: Controller N-1 or N-3 /Select
+ Bit 4: Controller N-1 or N-3 /Start
+ Bit 3: Controller N-1 or N-3 /Up
+ Bit 2: Controller N-1 or N-3 /Down
+ Bit 1: Controller N-1 or N-3 /Left
+ Bit 0: Controller N-1 or N-3 /Right
+
+ *Octet 2*
+
+ Bit 7: Controller N-1 or N-3 /A
+ Bit 6: Controller N-1 or N-3 /X
+ Bit 5: Controller N-1 or N-3 /L
+ Bit 4: Controller N-1 or N-3 /R
+ Bit 3: 1
+ Bit 2: 1
+ Bit 1: 1
+ Bit 0: 1
+
+ *Octet 3*
+
+ Bit 7: Controller N-2 or N-4 /B
+ Bit 6: Controller N-2 or N-4 /Y
+ Bit 5: Controller N-2 or N-4 /Select
+ Bit 4: Controller N-2 or N-4 /Start
+ Bit 3: Controller N-2 or N-4 /Up
+ Bit 2: Controller N-2 or N-4 /Down
+ Bit 1: Controller N-2 or N-4 /Left
+ Bit 0: Controller N-2 or N-4 /Right
+
+ *Octet 4*
+
+ Bit 7: Controller N-2 or N-4 /A
+ Bit 6: Controller N-2 or N-4 /X
+ Bit 5: Controller N-2 or N-4 /L
+ Bit 4: Controller N-2 or N-4 /R
+ Bit 3: 1
+ Bit 2: 1
+ Bit 1: 1
+ Bit 0: 1
+
+ *Controller N* is the controller port number on the console that the
+ Multitap is connected to. *Controller N-1...N-4* are the controller
+ ports *1...4* on the Multitap. Two Multitap ports are polled
+ simultaneously by the game - either *1 and 2*, or *3 and 4*. The I/O
+ Pin state in octet 0 MUST be *1* for multitap ports *1 and 2*, or *0*
+ for ports *3 and 4*.
+
4.3. N64 Controller Types
4.3.1. N64 Standard Controller
@@ -2055,14 +2125,14 @@ Table of Contents
*Octet 0*
- Bit 7: /A
- Bit 6: /Start
- Bit 5: /Up
- Bit 4: /Down
- Bit 3: /Left
- Bit 2: /Right
- Bit 1: /B
- Bit 0: /C
+ Bit 7: /Up
+ Bit 6: /Down
+ Bit 5: /Left
+ Bit 4: /Right
+ Bit 3: /B
+ Bit 2: /C
+ Bit 1: /A
+ Bit 0: /Start
4.8.2. Genesis (Mega Drive) 6-Button
@@ -2070,14 +2140,14 @@ Table of Contents
*Octet 0*
- Bit 7: /A
- Bit 6: /Start
- Bit 5: /Up
- Bit 4: /Down
- Bit 3: /Left
- Bit 2: /Right
- Bit 1: /B
- Bit 0: /C
+ Bit 7: /Up
+ Bit 6: /Down
+ Bit 5: /Left
+ Bit 4: /Right
+ Bit 3: /B
+ Bit 2: /C
+ Bit 1: /A
+ Bit 0: /Start
*Octet 1*
@@ -2137,7 +2207,7 @@ Table of Contents
Copyright Notice
- Copyright (c) 2021-2022, Vi Grey and Bigbass
+ Copyright (c) 2021-2023, Vi Grey, Bigbass, and rasteri
All rights reserved.
@@ -2170,10 +2240,13 @@ Copyright Notice
Authors' Addresses
Vi Grey
- VG Interactive
Email: vi@vigrey.com
URI: https://vigrey.com
Bigbass
URI: https://github.com/bigbass1997
+
+
+ rasteri
+ URI: https://github.com/rasteri
diff --git a/docs/tasd-spec-0001/draft-tasd-spec-0001.html b/docs/tasd-spec-0001/draft-tasd-spec-0001.html
index 60a7a65..5daf4c9 100644
--- a/docs/tasd-spec-0001/draft-tasd-spec-0001.html
+++ b/docs/tasd-spec-0001/draft-tasd-spec-0001.html
@@ -7,6 +7,7 @@
<title>TASD File Format Specification Version 1</title>
<meta content="Vi Grey" name="author">
<meta content="Bigbass" name="author">
+<meta content="rasteri" name="author">
<meta content='
The TASD file format is used for storing "Tool Assisted Speedrun" or "Tool Assisted Superplay" (TAS) data for TAS replay devices to replay on physical video game console hardware. The format is defined to be expandable for future needs. The format is also defined to be parsable by programs that do not understand portions of the format, whether that is due to incomplete support of the format specification or due to new features being added to later versions of the specification at a later date.
This document defines the file format specification for TASD files.
@@ -1206,7 +1207,7 @@ li > p:last-of-type:only-child {
<td class="right">July 2023</td>
</tr></thead>
<tfoot><tr>
-<td class="left">Grey &amp; Bigbass</td>
+<td class="left">Grey, et al.</td>
<td class="center">Informational</td>
<td class="right">[Page]</td>
</tr></tfoot>
@@ -1218,17 +1219,19 @@ li > p:last-of-type:only-child {
<dd class="workgroup">Independent TAS Console Replay Research Group</dd>
<dt class="label-published">Published:</dt>
<dd class="published">
-<time datetime="2023-07-03" class="published">3 July 2023</time>
+<time datetime="2023-07-06" class="published">6 July 2023</time>
</dd>
<dt class="label-authors">Authors:</dt>
<dd class="authors">
<div class="author">
<div class="author-name">V. Grey</div>
-<div class="org">VG Interactive</div>
</div>
<div class="author">
<div class="author-name">Bigbass</div>
</div>
+<div class="author">
+ <div class="author-name">rasteri</div>
+</div>
</dd>
</dl>
</div>
@@ -1494,6 +1497,9 @@ li > p:last-of-type:only-child {
<li class="compact toc ulBare ulEmpty" id="section-toc.1-1.4.2.2.2.2">
<p id="section-toc.1-1.4.2.2.2.2.1"><a href="#section-4.2.2" class="auto internal xref">4.2.2</a>.  <a href="#name-snes-mouse" class="internal xref">SNES Mouse</a></p>
</li>
+ <li class="compact toc ulBare ulEmpty" id="section-toc.1-1.4.2.2.2.3">
+ <p id="section-toc.1-1.4.2.2.2.3.1"><a href="#section-4.2.3" class="auto internal xref">4.2.3</a>.  <a href="#name-snes-super-multitap" class="internal xref">SNES Super Multitap</a></p>
+</li>
</ul>
</li>
<li class="compact toc ulBare ulEmpty" id="section-toc.1-1.4.2.3">
@@ -3922,6 +3928,188 @@ li > p:last-of-type:only-child {
<dd class="break"></dd>
</dl>
</section>
+<section id="section-4.2.3">
+ <h4 id="name-snes-super-multitap">
+<a href="#section-4.2.3" class="section-number selfRef">4.2.3. </a><a href="#name-snes-super-multitap" class="section-name selfRef">SNES Super Multitap</a>
+ </h4>
+<p id="section-4.2.3-1">Single Input Length: 5 Octets<a href="#section-4.2.3-1" class="pilcrow">¶</a></p>
+<p id="section-4.2.3-2"><strong>Octet 0</strong> :<a href="#section-4.2.3-2" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-3">
+ <dt id="section-4.2.3-3.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.2">1<a href="#section-4.2.3-3.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.4">1<a href="#section-4.2.3-3.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.6">1<a href="#section-4.2.3-3.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.8">1<a href="#section-4.2.3-3.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.10">1<a href="#section-4.2.3-3.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.12">1<a href="#section-4.2.3-3.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.14">1<a href="#section-4.2.3-3.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-3.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-3.16">I/O Pin State - <strong>1</strong> if Multitap ports <strong>1 and 2</strong> are being polled, <strong>0</strong> if ports <strong>3 and 4</strong> are.<a href="#section-4.2.3-3.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-4"><strong>Octet 1</strong><a href="#section-4.2.3-4" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-5">
+ <dt id="section-4.2.3-5.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.2">Controller N-1 or N-3 /B<a href="#section-4.2.3-5.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.4">Controller N-1 or N-3 /Y<a href="#section-4.2.3-5.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.6">Controller N-1 or N-3 /Select<a href="#section-4.2.3-5.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.8">Controller N-1 or N-3 /Start<a href="#section-4.2.3-5.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.10">Controller N-1 or N-3 /Up<a href="#section-4.2.3-5.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.12">Controller N-1 or N-3 /Down<a href="#section-4.2.3-5.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.14">Controller N-1 or N-3 /Left<a href="#section-4.2.3-5.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-5.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-5.16">Controller N-1 or N-3 /Right<a href="#section-4.2.3-5.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-6"><strong>Octet 2</strong><a href="#section-4.2.3-6" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-7">
+ <dt id="section-4.2.3-7.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.2">Controller N-1 or N-3 /A<a href="#section-4.2.3-7.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.4">Controller N-1 or N-3 /X<a href="#section-4.2.3-7.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.6">Controller N-1 or N-3 /L<a href="#section-4.2.3-7.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.8">Controller N-1 or N-3 /R<a href="#section-4.2.3-7.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.10">1<a href="#section-4.2.3-7.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.12">1<a href="#section-4.2.3-7.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.14">1<a href="#section-4.2.3-7.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-7.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-7.16">1<a href="#section-4.2.3-7.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-8"><strong>Octet 3</strong><a href="#section-4.2.3-8" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-9">
+ <dt id="section-4.2.3-9.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.2">Controller N-2 or N-4 /B<a href="#section-4.2.3-9.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.4">Controller N-2 or N-4 /Y<a href="#section-4.2.3-9.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.6">Controller N-2 or N-4 /Select<a href="#section-4.2.3-9.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.8">Controller N-2 or N-4 /Start<a href="#section-4.2.3-9.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.10">Controller N-2 or N-4 /Up<a href="#section-4.2.3-9.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.12">Controller N-2 or N-4 /Down<a href="#section-4.2.3-9.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.14">Controller N-2 or N-4 /Left<a href="#section-4.2.3-9.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-9.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-9.16">Controller N-2 or N-4 /Right<a href="#section-4.2.3-9.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-10"><strong>Octet 4</strong><a href="#section-4.2.3-10" class="pilcrow">¶</a></p>
+<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.2.3-11">
+ <dt id="section-4.2.3-11.1">Bit 7:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.2">Controller N-2 or N-4 /A<a href="#section-4.2.3-11.2" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.3">Bit 6:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.4">Controller N-2 or N-4 /X<a href="#section-4.2.3-11.4" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.5">Bit 5:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.6">Controller N-2 or N-4 /L<a href="#section-4.2.3-11.6" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.7">Bit 4:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.8">Controller N-2 or N-4 /R<a href="#section-4.2.3-11.8" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.9">Bit 3:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.10">1<a href="#section-4.2.3-11.10" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.11">Bit 2:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.12">1<a href="#section-4.2.3-11.12" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.13">Bit 1:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.14">1<a href="#section-4.2.3-11.14" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+<dt id="section-4.2.3-11.15">Bit 0:</dt>
+ <dd style="margin-left: 1.5em" id="section-4.2.3-11.16">1<a href="#section-4.2.3-11.16" class="pilcrow">¶</a>
+</dd>
+ <dd class="break"></dd>
+</dl>
+<p id="section-4.2.3-12"><strong>Controller N</strong> is the controller port number on the console that the Multitap is connected to. <strong>Controller N-1...N-4</strong> are the controller ports <strong>1...4</strong> on the Multitap. Two Multitap ports are polled simultaneously by the game - either <strong>1 and 2</strong>, or <strong>3 and 4</strong>. The I/O Pin state in octet 0 <span class="bcp14">MUST</span> be <strong>1</strong> for multitap ports <strong>1 and 2</strong>, or <strong>0</strong> for ports <strong>3 and 4</strong>.<a href="#section-4.2.3-12" class="pilcrow">¶</a></p>
+</section>
</section>
<section id="section-4.3">
<h3 id="name-n64-controller-types">
@@ -4820,35 +5008,35 @@ li > p:last-of-type:only-child {
<p id="section-4.8.1-2"><strong>Octet 0</strong><a href="#section-4.8.1-2" class="pilcrow">¶</a></p>
<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.8.1-3">
<dt id="section-4.8.1-3.1">Bit 7:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.2">/A<a href="#section-4.8.1-3.2" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.2">/Up<a href="#section-4.8.1-3.2" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.3">Bit 6:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.4">/Start<a href="#section-4.8.1-3.4" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.4">/Down<a href="#section-4.8.1-3.4" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.5">Bit 5:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.6">/Up<a href="#section-4.8.1-3.6" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.6">/Left<a href="#section-4.8.1-3.6" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.7">Bit 4:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.8">/Down<a href="#section-4.8.1-3.8" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.8">/Right<a href="#section-4.8.1-3.8" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.9">Bit 3:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.10">/Left<a href="#section-4.8.1-3.10" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.10">/B<a href="#section-4.8.1-3.10" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.11">Bit 2:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.12">/Right<a href="#section-4.8.1-3.12" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.12">/C<a href="#section-4.8.1-3.12" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.13">Bit 1:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.14">/B<a href="#section-4.8.1-3.14" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.14">/A<a href="#section-4.8.1-3.14" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.1-3.15">Bit 0:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.1-3.16">/C<a href="#section-4.8.1-3.16" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.1-3.16">/Start<a href="#section-4.8.1-3.16" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
</dl>
@@ -4861,35 +5049,35 @@ li > p:last-of-type:only-child {
<p id="section-4.8.2-2"><strong>Octet 0</strong><a href="#section-4.8.2-2" class="pilcrow">¶</a></p>
<span class="break"></span><dl class="dlCompact dlParallel" id="section-4.8.2-3">
<dt id="section-4.8.2-3.1">Bit 7:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.2">/A<a href="#section-4.8.2-3.2" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.2">/Up<a href="#section-4.8.2-3.2" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.3">Bit 6:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.4">/Start<a href="#section-4.8.2-3.4" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.4">/Down<a href="#section-4.8.2-3.4" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.5">Bit 5:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.6">/Up<a href="#section-4.8.2-3.6" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.6">/Left<a href="#section-4.8.2-3.6" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.7">Bit 4:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.8">/Down<a href="#section-4.8.2-3.8" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.8">/Right<a href="#section-4.8.2-3.8" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.9">Bit 3:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.10">/Left<a href="#section-4.8.2-3.10" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.10">/B<a href="#section-4.8.2-3.10" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.11">Bit 2:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.12">/Right<a href="#section-4.8.2-3.12" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.12">/C<a href="#section-4.8.2-3.12" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.13">Bit 1:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.14">/B<a href="#section-4.8.2-3.14" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.14">/A<a href="#section-4.8.2-3.14" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
<dt id="section-4.8.2-3.15">Bit 0:</dt>
- <dd style="margin-left: 1.5em" id="section-4.8.2-3.16">/C<a href="#section-4.8.2-3.16" class="pilcrow">¶</a>
+ <dd style="margin-left: 1.5em" id="section-4.8.2-3.16">/Start<a href="#section-4.8.2-3.16" class="pilcrow">¶</a>
</dd>
<dd class="break"></dd>
</dl>
@@ -5043,7 +5231,7 @@ li > p:last-of-type:only-child {
<h2 id="name-copyright-notice">
<a href="#name-copyright-notice" class="section-name selfRef">Copyright Notice</a>
</h2>
-<p id="appendix-A-1">Copyright (c) 2021-2022, Vi Grey and Bigbass<a href="#appendix-A-1" class="pilcrow">¶</a></p>
+<p id="appendix-A-1">Copyright (c) 2021-2023, Vi Grey, Bigbass, and rasteri<a href="#appendix-A-1" class="pilcrow">¶</a></p>
<p id="appendix-A-2">All rights reserved.<a href="#appendix-A-2" class="pilcrow">¶</a></p>
<p id="appendix-A-3">Redistribution and use of this documentation in source (XML format) and/or "compiled" forms (TXT, PDF, HTML, etc), with or without modification, are permitted provided that the following conditions are met:<a href="#appendix-A-3" class="pilcrow">¶</a></p>
<ol start="1" type="1" class="normal type-1" id="appendix-A-4">
@@ -5061,7 +5249,6 @@ li > p:last-of-type:only-child {
</h2>
<address class="vcard">
<div dir="auto" class="left"><span class="fn nameRole">Vi Grey</span></div>
-<div dir="auto" class="left"><span class="org">VG Interactive</span></div>
<div class="email">
<span>Email:</span>
<a href="mailto:vi@vigrey.com" class="email">vi@vigrey.com</a>
@@ -5078,6 +5265,13 @@ li > p:last-of-type:only-child {
<a href="https://github.com/bigbass1997" class="url">https://github.com/bigbass1997</a>
</div>
</address>
+<address class="vcard">
+ <div dir="auto" class="left"><span class="fn nameRole">rasteri</span></div>
+<div class="url">
+<span>URI:</span>
+<a href="https://github.com/rasteri" class="url">https://github.com/rasteri</a>
+</div>
+</address>
</section>
</div>
<script>const toc = document.getElementById("toc");
diff --git a/docs/tasd-spec-0001/draft-tasd-spec-0001.txt b/docs/tasd-spec-0001/draft-tasd-spec-0001.txt
index 655f2c7..cfac083 100644
--- a/docs/tasd-spec-0001/draft-tasd-spec-0001.txt
+++ b/docs/tasd-spec-0001/draft-tasd-spec-0001.txt
@@ -3,9 +3,11 @@
Independent TAS Console Replay Research Group V. Grey
- VG Interactive
+
Bigbass
- 3 July 2023
+
+ rasteri
+ 6 July 2023
TASD File Format Specification Version 1
@@ -100,6 +102,7 @@ Table of Contents
4.2. SNES Controller Types
4.2.1. SNES Standard Controller
4.2.2. SNES Mouse
+ 4.2.3. SNES Super Multitap
4.3. N64 Controller Types
4.3.1. N64 Standard Controller
4.3.2. N64 Standard Controller with Rumble
@@ -1716,6 +1719,73 @@ Table of Contents
Bits 7-1: /Horizontal displacement since last read
Bit 0: Direction (0: up; 1: down)
+4.2.3. SNES Super Multitap
+
+ Single Input Length: 5 Octets
+
+ *Octet 0* :
+
+ Bit 7: 1
+ Bit 6: 1
+ Bit 5: 1
+ Bit 4: 1
+ Bit 3: 1
+ Bit 2: 1
+ Bit 1: 1
+ Bit 0: I/O Pin State - *1* if Multitap ports *1 and 2* are being
+ polled, *0* if ports *3 and 4* are.
+
+ *Octet 1*
+
+ Bit 7: Controller N-1 or N-3 /B
+ Bit 6: Controller N-1 or N-3 /Y
+ Bit 5: Controller N-1 or N-3 /Select
+ Bit 4: Controller N-1 or N-3 /Start
+ Bit 3: Controller N-1 or N-3 /Up
+ Bit 2: Controller N-1 or N-3 /Down
+ Bit 1: Controller N-1 or N-3 /Left
+ Bit 0: Controller N-1 or N-3 /Right
+
+ *Octet 2*
+
+ Bit 7: Controller N-1 or N-3 /A
+ Bit 6: Controller N-1 or N-3 /X
+ Bit 5: Controller N-1 or N-3 /L
+ Bit 4: Controller N-1 or N-3 /R
+ Bit 3: 1
+ Bit 2: 1
+ Bit 1: 1
+ Bit 0: 1
+
+ *Octet 3*
+
+ Bit 7: Controller N-2 or N-4 /B
+ Bit 6: Controller N-2 or N-4 /Y
+ Bit 5: Controller N-2 or N-4 /Select
+ Bit 4: Controller N-2 or N-4 /Start
+ Bit 3: Controller N-2 or N-4 /Up
+ Bit 2: Controller N-2 or N-4 /Down
+ Bit 1: Controller N-2 or N-4 /Left
+ Bit 0: Controller N-2 or N-4 /Right
+
+ *Octet 4*
+
+ Bit 7: Controller N-2 or N-4 /A
+ Bit 6: Controller N-2 or N-4 /X
+ Bit 5: Controller N-2 or N-4 /L
+ Bit 4: Controller N-2 or N-4 /R
+ Bit 3: 1
+ Bit 2: 1
+ Bit 1: 1
+ Bit 0: 1
+
+ *Controller N* is the controller port number on the console that the
+ Multitap is connected to. *Controller N-1...N-4* are the controller
+ ports *1...4* on the Multitap. Two Multitap ports are polled
+ simultaneously by the game - either *1 and 2*, or *3 and 4*. The I/O
+ Pin state in octet 0 MUST be *1* for multitap ports *1 and 2*, or *0*
+ for ports *3 and 4*.
+
4.3. N64 Controller Types
4.3.1. N64 Standard Controller
@@ -2055,14 +2125,14 @@ Table of Contents
*Octet 0*
- Bit 7: /A
- Bit 6: /Start
- Bit 5: /Up
- Bit 4: /Down
- Bit 3: /Left
- Bit 2: /Right
- Bit 1: /B
- Bit 0: /C
+ Bit 7: /Up
+ Bit 6: /Down
+ Bit 5: /Left
+ Bit 4: /Right
+ Bit 3: /B
+ Bit 2: /C
+ Bit 1: /A
+ Bit 0: /Start
4.8.2. Genesis (Mega Drive) 6-Button
@@ -2070,14 +2140,14 @@ Table of Contents
*Octet 0*
- Bit 7: /A
- Bit 6: /Start
- Bit 5: /Up
- Bit 4: /Down
- Bit 3: /Left
- Bit 2: /Right
- Bit 1: /B
- Bit 0: /C
+ Bit 7: /Up
+ Bit 6: /Down
+ Bit 5: /Left
+ Bit 4: /Right
+ Bit 3: /B
+ Bit 2: /C
+ Bit 1: /A
+ Bit 0: /Start
*Octet 1*
@@ -2137,7 +2207,7 @@ Table of Contents
Copyright Notice
- Copyright (c) 2021-2022, Vi Grey and Bigbass
+ Copyright (c) 2021-2023, Vi Grey, Bigbass, and rasteri
All rights reserved.
@@ -2170,10 +2240,13 @@ Copyright Notice
Authors' Addresses
Vi Grey
- VG Interactive
Email: vi@vigrey.com
URI: https://vigrey.com
Bigbass
URI: https://github.com/bigbass1997
+
+
+ rasteri
+ URI: https://github.com/rasteri
diff --git a/src/docs/draft-tasd-spec-0001.xml b/src/docs/draft-tasd-spec-0001.xml
index 1bd0182..cf9d6df 100644
--- a/src/docs/draft-tasd-spec-0001.xml
+++ b/src/docs/draft-tasd-spec-0001.xml
@@ -17,7 +17,6 @@
<title abbrev="TASD File Format Specification">TASD File Format Specification Version 1</title>
<seriesInfo name="Internet-Draft" stream="independent" value="draft-tasd-v0001-00" status="informational"/>
<author fullname="Vi Grey" initials="V." surname="Grey">
- <organization>VG Interactive</organization>
<address>
<email>vi@vigrey.com</email>
<uri>https://vigrey.com</uri>
@@ -28,6 +27,11 @@
<uri>https://github.com/bigbass1997</uri>
</address>
</author>
+ <author fullname="rasteri" surname="rasteri">
+ <address>
+ <uri>https://github.com/rasteri</uri>
+ </address>
+ </author>
<date year="2023"/>
<area>General</area>
<workgroup>Independent TAS Console Replay Research Group</workgroup>
@@ -1448,7 +1452,7 @@
<dt>Bit 1:</dt><dd>1</dd>
<dt>Bit 0:</dt><dd>1</dd>
</dl>
- <t><strong>Controller N</strong> is the controller port number on the console that the Multitap is connected to. <strong>Controller N-1...N-4</strong> are the controller ports <strong>1...4</strong> on the Multitap. Two Multitap ports are polled simultaneously by the game - either <strong>1 and 2</strong>, or <strong>3 and 4</strong>. The I/O Pin state in octet 0 <strong>MUST</strong> be <strong>1</strong> for multitap ports <strong>1 and 2</strong>, or <strong>0</strong> for ports <strong>3 and 4</strong>.</t>
+ <t><strong>Controller N</strong> is the controller port number on the console that the Multitap is connected to. <strong>Controller N-1...N-4</strong> are the controller ports <strong>1...4</strong> on the Multitap. Two Multitap ports are polled simultaneously by the game - either <strong>1 and 2</strong>, or <strong>3 and 4</strong>. The I/O Pin state in octet 0 <bcp14>MUST</bcp14> be <strong>1</strong> for multitap ports <strong>1 and 2</strong>, or <strong>0</strong> for ports <strong>3 and 4</strong>.</t>
</section>
</section>
<section numbered="true" toc="default">
@@ -1878,7 +1882,7 @@
</references>
<section numbered="false" toc="default">
<name>Copyright Notice</name>
- <t>Copyright (c) 2021-2023, Vi Grey and Bigbass</t>
+ <t>Copyright (c) 2021-2023, Vi Grey, Bigbass, and rasteri</t>
<t>All rights reserved.</t>
<t>Redistribution and use of this documentation in source (XML format) and/or "compiled" forms (TXT, PDF, HTML, etc), with or without modification, are permitted provided that the following conditions are met:</t>
<ol>
@@ -1888,6 +1892,9 @@
<t>THIS DOCUMENTATION IS PROVIDED BY THE AUTHOR(S) "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</t>
</section>
<!-- Change Log
+
+draft 05 - 2023-07-06 VG surround MUST with <bcp14> tag instead of <strong> tag
+
draft 04 - 2023-07-06 Bigbass Reordered Genesis 3-button and 6-button controller formats to better align with real hardware
draft 03 - 2023-07-06 rasteri Add SNES Super Multitap input format
generated by cgit v1.2.3 (git 2.25.1) at 2026-10-15 09:17:10 +0000